CS5124XD8 ON Semiconductor, CS5124XD8 Datasheet - Page 8

• Manufacturer Part Number: CS5124XD8
• Description: IC CTRLR PWM CURRENT MODE 8-SOIC
• Manufacturer: ON Semiconductor

Specifications of CS5124XD8

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 440kHz
• Duty Cycle: 85%
• Voltage - Supply: 7.6 V ~ 20 V
• Buck: No
• Boost: No
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 440kHz
• Output Voltage: - 0.3 V to + 20 V
• Output Current: 200 mA
• Mounting Style: SMD/SMT
• Switching Frequency: 440 KHz
• Operating Supply Voltage: 7.7 V to 20 V
• Maximum Operating Temperature: + 135 C
• Fall Time: 25 ns
• Minimum Operating Temperature: - 40 C
• Rise Time: 45 ns
• Synchronous Pin: No
• Topology: Flyback, Forward
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

UVLO and Thermal Shutdown Interaction
same internal comparator. During high temperature
operation (T
thermal shutdown circuit. This interaction increases the
turn−on threshold (and hysteresis) of the UVLO circuit. If
the UVLO pin shuts down the IC during high temperature
operation, higher hysteresis (see hysteresis specification)
might be required to enable the IC.
BIAS Pin
main application diagram in Figure 1. In order to provide
adequate phase margin for the bias control loop, the pole
created by the series pass transistor and the V
capacitor should be kept above 10 kHz. The frequency of
this pole can be calculated by Formula (1).
Pole Frequency +
regulated V
show up as poor line regulation with a low value pull−up
resistor. Typical regulated V
shown in Figure 3.
impedance node. Care should be taken during PCB layout to
avoid connections that could couple noise into this node. To
ensure adequate design margin between the regulated V
and the Low V
differential between the two values is specified (see
electrical characteristcs).
Gate Drive
13.5 V) over a range of MOSFET input capacitance if the
gate resistor value is kept low. Figure 5 shows the high gate
drive level vs. the series gate resistance with V
driving an IRF220.
The UVLO pin and thermal shutdown circuit share the
The bias pin can be used to control V
The Line BIAS pin shows a significant change in the
8.3
8.2
8.1
8.0
7.9
The BIAS pin and associated components form a high
Rail to rail gate driver operation can be obtained (up to
5.0 m
Figure 3. Regulated V
CC
J
10 m
> 100 C) the UVLO pin will interact with the
voltage when sinking large currents. This will
CC
Transconductance of pass Transistor
Lockout voltage, a guaranteed minimum
Bias Current (I
20 m
2
CC
CC
vs. BIAS Sink Current
vs BIAS pin sink current is
p
BIAS
50 m
C V(CC)
)
CC
100 m
as shown in the
APPLICATION INFORMATION
CC
CC
= 8.0 V
bypass
http://onsemi.com
200 m
(1)
CC
8
couple current into the gate driver through the gate to drain
capacitance. If this current is kept within absolute maximum
ratings for the GATE pin it will not damage the IC. However
if a high negative dv/dt coincides with the start of a PWM
duty cycle, there will be small variations in oscillator
frequency due to current in the controller substrate. If
required, this can be avoided by choosing the transformer
ratio and reset circuit so that a high dv/dt does not coincide
with the start of a PWM cycle, or by clamping the negative
voltage on the GATE pin with a Schottky diode
First Current Sense Threshold
controlled by the level of the V
control loop) and the current sense network. Once the signal
on the I
the PWM cycle terminates. During high output currents the
V
current sense threshold determines the maximum signal
allowed on the I
terminated. Under this condition the maximum peak current
is determined by the V
ramp, the PWM comparator offset voltage and the PWM on
time. The nominal first current threshold varies with on time
and can be calculated from Formulas (2) and (3) below.
to exceed the first threshold, the PWM cycle terminates
early and the converter begins to function more like a current
source. The current sense network must be chosen so that the
peak current during normal operation does not exceed the
first current sense threshold.
Second Current Sense Threshold
from overheating by switching to a low duty cycle mode
when there are abnormally high fast rise currents in the
1st Threshold +
FB
A large negative dv/dt on the power MOSFET drain will
During normal operation the peak primary current is
When the output current is high enough for the I
The second threshold is intended to protect the converter
8.5
8.0
7.5
7.0
6.5
6.0
Figure 4. Gate Drive vs. Gate Resistor Driving an
pin will rise until it reaches the V
0
SENSE
pin exceeds the level determined by V
0.3
2.9 V * 170 mV ms
SENSE
IRF220 (V
FB
Gate Resistor Value
0.5
pin before the PWM cycle is
Clamp, the slope compensation
10
CC
FB
= 8.0 V)
pin (as determined by the
T ON
2.5
FB
* 60 mV
clamp. The first
5.0
SENSE
FB
pin
(2)
pin
11