ISL6568CRZ-TR5184 Intersil, ISL6568CRZ-TR5184 Datasheet - Page 16

• Manufacturer Part Number: ISL6568CRZ-TR5184
• Description: IC CTRLR PWM 2PHASE BUCK 32-QFN
• Manufacturer: Intersil

Specifications of ISL6568CRZ-TR5184

• Applications: Controller, Intel VRM9, VRM10, and AMD Hammer Applications
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.84 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL6568CRZ-TR5184; ISL6568CRZ-TR5184TR

Once the desired output offset voltage has been determined,
use the following formulas to set R
For Positive Offset (connect R
R
OFS
R
V
R
V
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
OFS
OFS
OFS
OFS
+
-
+
-
VDIFF
VDIFF
VCC
=
I
OFS
--------------------------
V
GND
0.5 R
R
R
I
OFS
OFFSET
FB
FB
OFS
OFS
FB
FB
×
PROGRAMMING
PROGRAMMING
FB
ISL6568
ISL6568
VREF
VREF
16
OFS
OFS
to GND):
:
E/A
GND
E/A
GND
+
+
-
-
0.5V
0.5V
VCC
VCC
(EQ. 8)
+
+
-
-
1.5V
1.5V
ISL6568
For Negative Offset (connect R
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the core-
voltage regulator to do this by making changes to the VID
inputs. The core-voltage regulator is required to monitor the
DAC inputs and respond to on-the-fly VID changes in a
controlled manner, supervising a safe output voltage transition
without discontinuity or disruption.
The DAC mode the ISL6568 is operating in determines how
the controller responds to a dynamic VID change. When in
VRM10 mode the ISL6568 checks the VID inputs six times
every switching cycle. If a new code is established and it
stays the same for 3 consecutive readings, the ISL6568
recognizes the change and increments the reference.
Specific to VRM10, the processor controls the VID
transitions and is responsible for incrementing or
decrementing one VID step at a time. In VRM10 setting, the
ISL6568 will immediately change the reference to the new
requested value as soon as the request is validated; in
cases where the reference step is too large, the sudden
change can trigger overcurrent or overvoltage events.
In order to ensure the smooth transition of output voltage
during a VRM10 VID change, a VID step change smoothing
network is required for an ISL6568 based voltage regulator.
This network is composed of a 1kΩ internal resistor between
the output of DAC and the capacitor C
pin and ground. The selection of C
duration for 1 bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at 1
bit every T
given by Equation 10.
As an example, for a VID step change rate of 5µs per bit, the
value of C
When running in VRM9 or AMD Hammer operation, the
ISL6568 responds slightly differently to a dynamic VID change
than when in VRM10 mode. In these modes the VID code can
be changed by more than a 1-bit step at a time. Once the
controller receives the new VID code it waits half of a phase
cycle and then begins slewing the DAC 12.5mV every phase
cycle, until the VID and DAC are equal. Thus, the total time
required for a VID change, t
switching frequency (f
the time required to register the VID change. The one-cycle
addition in the t
VID code change may occur up to one full switching cycle
before being recognized. The approximate time required for a
ISL6568-based converter in AMD Hammer configuration
C
R
REF
OFS
=
=
0.004X T
1.5 R
--------------------------
V
REF
OFFSET
VID
×
, the relationship between C
is 22nF based on Equation 10.
DVID
FB
VID
equation is due to the possibility that the
S
), the size of the change (∆V
DVID
OFS
, is dependent on the
REF
to VCC):
REF
is based on the time
, between the REF
REF
and T
VID
March 9, 2006
VID
(EQ. 10)
), and
FN9187.4
(EQ. 9)
is