ISL6568CRZ-TR5184 Intersil, ISL6568CRZ-TR5184 Datasheet - Page 22

• Manufacturer Part Number: ISL6568CRZ-TR5184
• Description: IC CTRLR PWM 2PHASE BUCK 32-QFN
• Manufacturer: Intersil

Specifications of ISL6568CRZ-TR5184

• Applications: Controller, Intel VRM9, VRM10, and AMD Hammer Applications
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.84 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL6568CRZ-TR5184; ISL6568CRZ-TR5184TR

The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in the
controller itself is the power dissipated in the upper drive path
resistance, P
and in the boot strap diode, P
be dissipated by the external gate resistors (R
the internal gate resistors (R
Figures 15 and 16 show the typical upper and lower gate
drives’ turn-on transition path. The total power dissipation in the
controller itself, P
Current Balancing Component Selection
The ISL6568 senses the channel load current by sampling
the voltage across the lower MOSFET r
Figure 17. The ISEN pins are denoted ISEN1 and ISEN2.
The resistors connected between these pins and the
respective phase nodes determine the gains in the channel-
current balance loop.
P
P
P
R
P
FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
DR
DR_UP
DR_LOW
EXT1
BOOT
PVCC
=
P
=
=
R
DR_UP
=
R
R
LO2
=
P
---------------------
HI2



G1
Qg_Q1
--------------------------------------
R
DR_UP



HI1
--------------------------------------
R
3
+
HI2
+
R
-------------
DR
R
N
+
P
GI1
HI1
Q1
R
, the lower drive path resistance, P
R
+
DR_LOW
, can be roughly estimated as:
LGATE
HI2
EXT1
R
EXT2
+
GI1
+
--------------------------------------- -
R
+
BOOT
22
LO1
--------------------------------------- -
R
P
R
R
LO2
G2
and R
BOOT
EXT2
R
G
+
LO1
R
. The rest of the power will
+
R
LO2
R
C
EXT1
R
GI2
GD
GI2
+
=
C
EXT2
(
R
GS
I
DS(ON)
) of the MOSFETs.
Q
G2



•
•



S
VCC
+
G1
P
---------------------
•
R
-------------
Qg_Q1
N
P
---------------------
and R
GI2
, as shown in
Q2
Qg_Q2
D
3
)
2
Q2
C
DR_UP
DS
G2
(EQ. 23)
) and
,
ISL6568
Select values for these resistors based on the room
temperature r
operating current, I
Equation 24.
In certain circumstances, it may be necessary to adjust the
value of one or more ISEN resistors. When the components of
one or more channels are inhibited from effectively dissipating
their heat so that the affected channels run hotter than
desired, choose new, smaller values of R
phases (see the section entitled Channel-Current Balance).
Choose R
temperature rise in order to cause proportionally less current
to flow in the hotter phase.
In Equation 25, make sure that ∆T
rise above the ambient temperature, and ∆T
temperature rise above the ambient temperature. While a
single adjustment according to Equation 25 is usually
sufficient, it may occasionally be necessary to adjust R
two or more times to achieve optimal thermal balance
between all channels.
Load Line Regulation Component Selection (DCR
Current Sensing)
For accurate load line regulation, the ISL6568 senses the
total output current by detecting the voltage across the
output inductor DCR of each channel (As described in the
Load Line Regulation section). As Figure 18 illustrates, an
R-C network is required to accurately sense the inductor
DCR voltage and convert this information into a “droop”
voltage, which is proportional to the total output current.
R
R
FIGURE 17. ISL6568 INTERNAL AND EXTERNAL CURRENT-
ISEN
ISEN 2 ,
ISL6568
=
=
---------------------- -
50 10
r
ISEN,2
DS ON
R
×
ISEN
(
SENSING CIRCUITRY
DS(ON)
–
6
)
in proportion to the desired decrease in
ISEN(n)
∆T
----------
∆T
I
------- -
FL
FL
N
CHANNEL N
LOWER MOSFET
2
1
of the lower MOSFETs; the full-load
; and the number of phases, N using
R
ISEN
V
IN
+
2
CHANNEL N
UPPER MOSFET
-
I
L
is the desired temperature
r
DS ON
I
L
(
ISEN
1
)
is the measured
for the affected
March 9, 2006
(EQ. 24)
(EQ. 25)
ISEN
FN9187.4