LTC1736IG Linear Technology, LTC1736IG Datasheet - Page 12

• Manufacturer Part Number: LTC1736IG
• Description: IC REG SW SYNC STEPDWN HE 24SSOP
• Manufacturer: Linear Technology

Specifications of LTC1736IG

• Applications: Converter, Intel Pentium® II, III
• Voltage - Input: 3.5 ~ 36 V
• Number Of Outputs: 1
• Voltage - Output: 0.93 ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC1736
APPLICATIO S I FOR ATIO
molypermalloy or Kool M
independent of core size for a fixed inductor value, but it
is very dependent on the inductance selected. As induc-
tance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool M . Toroids are very space efficient,
especially when you can use several layers of wire. Be-
cause they generally lack a bobbin, mounting is more
difficult. However, designs for surface mount are available
that do not increase the height significantly.
Power MOSFET and D1 Selection
Two external power MOSFETs must be selected for use
with the LTC1736: An N-channel MOSFET for the top
(main) switch and an N-channel MOSFET for the bottom
(synchronous) switch.
The peak-to-peak gate drive levels are set by the INTV
voltage. This voltage is typically 5.2V during start-up. (See
EXTV
old MOSFETs must be used in most LTC1736 applica-
tions. The only exception is when low input voltage is
expected (V
MOSFETs (V
attention to the BV
well; most of the logic level MOSFETs are limited to 30V or
less.
Selection criteria for the power MOSFETs include the “ON”
resistance R
input voltage and maximum output current. When the
LTC1736 is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
12
CC
Pin Connection.) Consequently, logic-level thresh-
IN
DS(ON)
GS(TH)
< 5V); then, sublogic level threshold
DSS
, reverse transfer capacitance C
U
< 3V) should be used. Pay close
specification for the MOSFETs as
U
®
cores. Actual core loss is
W
U
RSS
CC
,
The MOSFET power dissipations at maximum output
current are given by:
where is the temperature dependency of R
is a constant inversely related to the gate drive current.
Both MOSFETs have I
N-Channel equation includes an additional term for tran-
sition losses, which are highest at high input voltages. For
V
with larger MOSFETs, while for V
losses rapidly increase to the point that the use of a higher
R
efficiency. The synchronous MOSFET losses are greatest
at high input voltage or during a short circuit when the duty
cycle in this switch is nearly 100%.
The term (1 + ) is generally given for a MOSFET in the
form of a normalized R
voltage MOSFETs. C
characteristics. The constant k = 1.7 can be used to
estimate the contributions of the two terms in the main
switch dissipation equation.
The Schottky diode D1 shown in Figure 1 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on and storing charge during the
dead-time, which could cost as much as 1% in efficiency.
A 3A Schottky is generally a good size for 10A to 12A
regulators due to the relatively small average current.
Kool M is a registered trademark of Magnetics, Inc.
IN
DS(ON)
= 0.005/ C can be used as an approximation for low
Main Switch Duty Cycle
P
Synchronous Switch Duty Cycle
P
< 20V the high current efficiency generally improves
SYNC
MAIN
device with lower C
k V
V
V
V
OUT
IN
IN
IN
–
V
IN
V
2
I
MAX
OUT
RSS
I
MAX
DS(ON)
I
2
is usually specified in the MOSFET
MAX
2
1
R losses while the topside
C
RSS
RSS
2
V
vs Temperature curve, but
V
1
OUT
R
IN
actually provides higher
DS ON
f
IN
(
> 20V the transition
R
)
DS ON
V
IN
(
–
V
IN
)
DS(ON)
V
OUT
and k