L6756D STMicroelectronics, L6756D Datasheet - Page 28

• Manufacturer Part Number: L6756D
• Description: IC CTLR 2/3/4PH BUCK 40-VFQFPN
• Manufacturer: STMicroelectronics

Specifications of L6756D

• Applications: Controller, Intel VR10, VR11, VR11.1
• Voltage - Input: 12V
• Number Of Outputs: 4
• Voltage - Output: 0.3 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Output Voltage: 3 V
• Input Voltage: - 0.3 V to + 15 V
• Switching Frequency: 185 KHz to 215 KHz
• Operating Temperature Range: - 40 C to + 150 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Low power-state management and PSI#
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Caution:
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Low power-state management and PSI#
PSI# is an active-low input that can be set by the CPU to allow the regulator to enter power-
saving mode to maximize the system efficiency when in light-load conditions. The controller
constantly monitors the PSI_A pin to define the PSI strategy, that is the action performed by
the controller when PSI# is asserted. According to
voltages on PSI_A, it is possible to configure the device to work at one or two phases while
PSI# is asserted. The device can also be configured to take no action so phase number will
not change after PSI# assertion.
In case the phase number is changed, the device will disable one or more phases by setting
in HiZ the relative PWM and re-configuring the internal phase-shift to maintain the
interleaving. Furthermore, the internal current-sharing will be adjusted to consider the phase
number reduction. ENDRV will remain asserted.
When PSI# is de-asserted, the device will return to the original configuration.
Start-up is performed with all the configured phases enabled. In case of DVID transitions,
the device will use all the phases available to perform the transition coming back to the PSI
reduced number of phases after the transition has.
PSI Strategy is continuously monitored across PSI_A pin.
When PSI_A is set for working at 2phases when PSI# is asserted, the IC will work as if
configured for 2phases so enabling only Phase1 and Phase3.
Table 9.
Figure 12. System efficiency enhancement by PSI#
100 kΩ to VREF
GND / Open
to VREF
PSI_A
PSI strategy
No strategy.
IC will work in VR11 mode
Phase number set to 2 while PSI# is asserted (only phase1
and Phase3 are active).
Phase number set to 1 while PSI# is asserted (only phase1
is active).
PSI Strategy
Table
9, by programming different
PSI#/VR10
VR10
PSI#
L6756D