ISL6556BCBZ Intersil, ISL6556BCBZ Datasheet
ISL6556BCBZ
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ISL6556BCBZ Summary of contents
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... ISL6556B uses 5V bias and has a built-in shunt regulator to allow 12V bias using only a small external limiting resistor. Ordering Information PART NUMBER TEMP. (°C) PACKAGE ISL6556BCB SOIC ISL6556BCBZ SOIC (Pb-free) M28.3 (Note) ISL6556BCBZA SOIC Tape and -T (Note) Reel (Pb-free) ISL6556BCR 5x5B QFN ISL6556BCRZ 5x5B QFN (Pb-free) (Note) * Add “ ...
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Pinouts 32 LEAD QFN TOP VIEW VID3 1 2 VID2 3 VID1 4 VID0 5 VID12.5 6 OFS 7 TCOMP REF ISL6556B PWM4 ...
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ISL6565BCB Block Diagram VDIFF PGOOD RGND x1 VSEN OVP +200mV OFS OFFSET REF VID4 VID3 DYNAMIC VID2 VID VID1 D/A VID0 VID12.5 COMP FB TCOMP T 3 ISL6556B OVP VCC OVP R S POWER-ON LATCH RESET (POR) Q SOFT-START CLOCK ...
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ISL6565BCR Block Diagram VDIFF PGOOD RGND x1 VSEN OVP +200mV OFS OFFSET OFSOUT REF VID4 VID3 DYNAMIC VID2 VID VID1 D/A VID0 VID12.5 COMP FB TCOMP T 4 ISL6556B OVP VCC OVP R S POWER-ON LATCH RESET (POR) Q SOFT-START ...
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Typical Application of ISL6556BCB +5V FB COMP VCC TCOMP VDIFF VSEN RGND REF PGOOD OVP ISL6556BCB PWM1 VID4 ISEN1 VID3 PWM2 VID2 ISEN2 VID1 PWM3 VID0 ISEN3 VID12.5 PWM4 OFS FS ISEN4 EN GND R T VID_PGOOD (BUFFERED) 5 ISL6556B ...
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Typical Application of ISL6556BCR +5V COMP VCC FB OFSOUT VDIFF TCOMP VSEN RGND PGOOD REF OVP ISL6556BCR VID4 ISEN1 VID3 PWM1 VID2 PWM2 ISEN2 VID1 PWM3 VID0 ISEN3 VID12.5 PWM4 OFS FS ISEN4 GND ENLL +12V VID_PGOOD ...
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Absolute Maximum Ratings Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V ...
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Electrical Specifications Operating Conditions: VCC = 5V or ICC < 25mA (Note 4), T Unless Otherwise Specified. (Continued) PARAMETER PIN-ADJUSTABLE OFFSET Voltage at OFS pin OSCILLATOR Accuracy Adjustment Range Sawtooth Amplitude Max Duty Cycle ERROR AMPLIFIER Open-Loop Gain Open-Loop Bandwidth ...
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... PWM1, PWM2, PWM3, PWM4 - Pulse-width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM3 and PWM4. Tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to configure for 3-phase operation. ...
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Operation Multi-Phase Power Conversion Microprocessor load current profiles have changed to the point that the advantages of multi-phase power conversion are impossible to ignore. The technical challenges associated with producing a single-phase converter which is both cost- effective and thermally ...
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Figures 14, 16 and 16 in the section entitled Input Capacitor Selection can be used to determine the input-capacitor RMS current based on load current, duty cycle, and the number of channels. They are provided as aids in determining the ...
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... ISL6556B The output of the error amplifier, V sawtooth waveform to generate the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. The internal and external circuitry that controls voltage regulation is illustrated in Figure 5. ...
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TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES VID4 VID3 VID2 VID1 VID0 ...
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The magnitude of the spike is dictated by the ESR and ESL of the output capacitors selected. By positioning the no-load voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower limit. ...
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VID changes in a controlled manner. Supervising the safe output voltage transition within the DAC range of the processor without discontinuity or disruption is a necessary function of the core-voltage regulator. The ISL6556B checks the VID inputs six times ...
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... ICs reach their POR level before the ISL6556B becomes enabled. The schematic in Figure 8 demonstrates sequencing the ISL6556B with the HIP660X family of Intersil MOSFET drivers, which require 12V bias. 3. (ISL6556BCR only) The voltage on ENLL must be logic high to enable the controller. This pin is typically connected to the VID_PGOOD ...
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... VSEN falls below 0.6V with valid VCC or 1.5V otherwise. This causes the Intersil drivers to turn on the lower MOSFETs and pull the output voltage below a level that might cause damage to the load. The PWM outputs remain low until VDIFF falls to the programmed DAC level when they enter a high-impedance state ...
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... It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications. ...
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Current Sensing The ISEN pins are denoted ISEN1, ISEN2, ISEN3 and ISEN4. The resistors connected between these pins and the respective phase nodes determine the gains in the load-line regulation loop and the channel-current balance loop as well as setting ...
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ESR Case 2: 2π 2π -------------------------------------------- 0.75V ------------------------------------------------------------ - C ...
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Input Supply Voltage Selection The VCC input of the ISL6556B can be connected either directly to a +5V supply or through a current limiting resistor to a +12V supply. An integrated 5.8V shunt regulator maintains the voltage on the VCC ...
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... IN between the components is minimized while creating the PHASE plane. Place the Intersil MOSFET driver IC as close as possible to the MOSFETs they control to reduce the parasitic impedances due to trace length between critical driver input and output signals. If possible, duplicate the same placement of these components for each phase. ...
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Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...