ISL6217CVZ-T Intersil, ISL6217CVZ-T Datasheet - Page 10
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ISL6217CVZ-T
Manufacturer Part Number
ISL6217CVZ-T
Description
IC CTRLR PWM INTEL PENT 38-TSSOP
Manufacturer
Intersil
Datasheet
1.ISL6217CVZ.pdf
(19 pages)
Specifications of ISL6217CVZ-T
Applications
Controller, Intel Pentium® IMVP-IV, IMVP+
Voltage - Input
5.5 ~ 25 V
Number Of Outputs
1
Operating Temperature
-10°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
38-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Output
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISL6217CVZ-T
Manufacturer:
INTER
Quantity:
2 500
Company:
Part Number:
ISL6217CVZ-T
Manufacturer:
NS
Quantity:
2 500
Table 1.
VID5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
VID4
IMPV-IV VID CODES
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
VID2
10
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V DAC
1.708
1.692
1.676
1.660
1.644
1.628
1.612
1.596
1.580
1.564
1.548
1.532
1.516
1.500
1.484
1.468
1.452
1.436
1.420
1.404
1.388
1.372
1.356
1.340
1.324
1.308
1.292
1.276
1.260
1.244
1.228
1.212
1.196
1.180
1.164
1.148
1.132
1.116
1.100
1.084
1.068
1.052
ISL6217
Active, Deep Sleep and Deeper Sleep Modes
The ISL6217 Multi-Phase Controller is designed to control
the CORE output voltage as per the IMVP-IV™ and and
IMVP-IV+™ specifications for Active, Deep Sleep, and
Deeper Sleep Modes of Operation.
After initial start-up, a logic high signal on DSEN# and a
logic low signal on DRSEN signals the ISL6217 to operate
in Active mode (Refer to Table 2). This mode will recognize
VID code changes and regulate the output voltage to these
command voltages
Table 1.
Table 2.
VID5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
STP_CPU#
DSEN# -
1
0
0
1
VID4
IMPV-IV VID CODES
OUTPUT VOLTAGE AS A FUNCTION OF DSEN# AND
DRSEN LOGIC STATES
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
DPRSLPVR
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DRSEN -
0
0
1
1
VID2
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Deeper Sleep
Deeper Sleep
OPERATION
Deep Sleep
MODE OF
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Active
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V DAC
VOLTAGE
1.036
1.020
1.004
0.988
0.972
0.956
0.940
0.924
0.908
0.892
0.876
0.860
0.844
0.828
0.812
0.796
0.780
0.764
0.748
0.732
0.716
0.700
OUTPUT
DRSV
DRSV
DSV
VID