ISL6265AHRTZ-T Intersil, ISL6265AHRTZ-T Datasheet - Page 8

IC CTRLR MULTI-OUTPUT 48-TQFN

ISL6265AHRTZ-T

Manufacturer Part Number
ISL6265AHRTZ-T
Description
IC CTRLR MULTI-OUTPUT 48-TQFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6265AHRTZ-T

Applications
Controller, AMD SVI Capable Mobile
Voltage - Input
5 ~ 24 V
Number Of Outputs
3
Voltage - Output
0.5 ~ 1.55 V
Operating Temperature
-10°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
48-TQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL6265AHRTZ-T
Manufacturer:
HONEYWELL
Quantity:
100
Part Number:
ISL6265AHRTZ-T
Manufacturer:
INTERSIL
Quantity:
8 000
Part Number:
ISL6265AHRTZ-T
Manufacturer:
INTERSIL
Quantity:
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Electrical Specifications
NOTES:
ISL6265A Gate Driver Timing Diagram
OFFSET FUNCTION
OFS Pin Voltage For Droop Enabling
FB Pin Source Current
OFS Pin Voltage Threshold for VFIX
Mode and No Droop Operation
OFS Pin Voltage Threshold for SVI
Mode and No Droop Operation
OFS Bias
LOGIC INPUTS
ENABLE Low Threshold
ENABLE High Threshold
ENABLE Leakage Current
SVI INTERFACE
PWROK Input Low Threshold
PWROK Input High Threshold
SVC, SVD Input HIGH (VIH)
SVC, SVD Input LOW (VIL)
Schmitt Trigger Input Hysteresis
SVD Low Level Output Voltage
SVC, SVD Leakage
DIFF AMP
Accuracy
3. Limits should be considered typical and are not production tested.
4. Limits established by characterization and are not production tested.
PARAMETER
UGATE
LGATE
PWM
t
FL
8
VCC = PVCC = 5V, V
MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested (Continued)
1V
t
PDHU
SYMBOL
V
V
V
V
V
IH(3.3V)
IL(3.3V)
I
OFS
I
OFS
OFS
OFS
FB
t
R
I
1.8V < OFS < VCC
Logic input is low
Logic input is high at 3.3V
3mA Sink Current
EN = 0V, SVC, SVD = 0V
EN = 5V, SVC, SVD = 1.8V
VSEN = 0.5V to 1.55V; RTN = 0 ±0.1V
RU
OFS
OFS
IN
= 10µA
= 12V, T
= 240kΩ (OFS pin to GND)
ISL6265A
A
= -10°C to +100°C, Unless Otherwise Specified. Parameters with MIN and/or
1V
t
PDHL
TEST CONDITIONS
t
FU
t
RL
MIN
1.18
1.05
9.0
2.0
-1
-2
-
-
-
-
-
-
-
-
-
-
-
-
< -100
< -100
TYP
1.35
0.65
0.87
0.68
0.19
1.2
9.9
1.8
4.0
4.0
1.6
0.9
0.1
0
0
-
0.285
MAX
1.22
10.8
0.45
0.9
0.8
1
2
-
-
-
-
-
-
-
-
-
-
May 11, 2009
FN6884.0
UNITS
mV
µA
µA
µA
µA
nA
nA
V
V
V
V
V
V
V
V
V
V
V

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