NCP5318FTR2G ON Semiconductor, NCP5318FTR2G Datasheet - Page 21

• Manufacturer Part Number: NCP5318FTR2G
• Description: IC CTLR CPU 2/3/4 PHASE 32-LQFP
• Manufacturer: ON Semiconductor

Specifications of NCP5318FTR2G

• Applications: Controller, CPU
• Voltage - Input: 9.5 ~ 13.2 V
• Number Of Outputs: 4
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Switching Frequency: 1 MHz
• Mounting Style: SMD/SMT
• Primary Input Voltage: 18V
• No. Of Pins: 32
• Operating Temperature Range: 0°C To +70°C
• Termination Type: SMD
• Supply Voltage Min: 12V
• Packaging Type: Tape And Reel
• Peak Reflow Compatible (260 C): Yes
• Frequency: 1MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP5318FTR2G; NCP5318FTR2GOSTR

Adjusting the Number of Phases
architecture. Designers may choose any number of phases
up to four. The phase delay is automatically adjusted to
match the number of phases that will be used. This feature
allows the designer to select the number of phases required
for a particular application.
a 90 degree delay between pulses. No special connections
are required. Three−phase operation is achieved by
disabling phase 4. Tie together CS4N and CS4P, and then
pull both pins to V
to switch, but now there will be a 120 degree delay between
phases. The phase firing order will become 1−2−3.
First, the designer must choose the proper phases. Two phase
operation must use phases 2 and 4 by tying CS1N, CS1P,
CS3N and CS3P to ground. This will then use phases 2 and
4 to control gate drivers. The other gate control outputs may
switch, so leave them unconnected.
as the switch controller. Connect CS2P and CS2N pins to the
current sense circuit, and gate control output 2 to the gate
driver IC input. Tie all other CSxx pins together and connect
them to ground.
Design Procedure
1. Setting the Switching Frequency
operating frequency for all phases of the converter. The
frequency can be set for either the three phase or four phase
mode by using Figure 7, “Oscillator Frequency versus Total
R
frequency and the number of phases, use the figure to
determine the necessary resistance. If two phase operation
is desired, use the value given for four phase operation.
voltage can be used as the reference for the overcurrent limit
set point on the I
appropriate division ratio to give the desired I
and total resistance to set the operating frequency. Since
loading by the I
will not be affected.
2. Output Capacitor Selection
inductors and provide a low impedance for transient load
current changes. Typically, microprocessor applications
require both bulk (polymer, aluminum, or tantalum
electrolytic) and low impedance, high frequency (ceramic)
types of capacitors. The bulk capacitors provide “hold up”
during transient loading until phase currents ramp up or
down. The low impedance capacitors reduce steady−state
ripple voltage and bypass the bulk capacitance for fast
output current changes.
OSC
The NCP5318 is designed with a selectable−phase
Four−phase operation is standard. All phases switch with
Two− and single−phase operation may be realized as well.
Single phase is best accomplished by using only Phase 2
The total resistance from R
The voltage from R
The output capacitors filter the current from the output
Value”. After choosing the desired operating
LIM
LIM
CC
pin is very small, the frequency selection
pin. Design a voltage divider with the
. The remaining phases will continue
OSC
is closely regulated at 1.0 V. This
OSC
to ground sets the
LIM
voltage
http://onsemi.com
21
capacitors so as to meet the peak transient requirements. The
formula below can be used to provide a starting point for the
minimum number of bulk capacitors (NB
the voltage change during a load transient according to:
output capacitors in parallel. Capacitor manufacturers do
not always specify the ESL of their components and it is
affected by the inductance added by the PCB layout.
Therefore, it is necessary to start a design with slightly more
than the minimum number of bulk and ceramic capacitors
and perform transient testing to determine the final number
of bulk capacitors.
(DVID), by which the VID codes are stepped up or down to
a new desired output voltage. Timing requirements for when
the output must be in regulation further complicates output
capacitor selection. The ideal output capacitor selection has
low ESR and low capacitance. Too much output capacitance
will make it difficult to meet DVID timing specifications;
too much ESR will complicate the transient solution. The
Sanyo 4SEPC560 and Panasonic EEU−FL provide a good
balance of capacitance vs. ESR.
number of ceramic capacitors, which may need adjustment
to meet ripple voltage requirements. The output voltage
ripple can be calculated using the output inductor value
derived in the following section (L
bulk output capacitors (NB
V OUT,P * P + (ESRperbulkcap. NB OUT,MIN )
more than one phase on at any time. The second term in
Equation 3 is the total ripple current seen by the output
capacitors. The total output ripple current is the “time
summation” of the four individual phase currents that are 90
degrees out−of−phase. As the inductor current in one phase
ramps upward, current in the other phases ramp downward
and provides a canceling of currents during part of the
switching cycle. Therefore, the total output ripple current
and voltage are reduced in a multi−phase converter.
) V IN
[ ( V IN * #Phase
The designer must determine the number of bulk
The ESL of the bulk plus ceramic capacitors also affects
where ESL is the equivalent ESL of all bulk and ceramic
Intel processor specifications discuss “DynamicVID”
Microprocessor manufacturers often specify a minimum
This formula assumes steady−state conditions with no
NB OUT,MIN + ESR per capacitor
DV O,MAX + (
ESLperceramiccap. NC OUT,MIN L O,MIN
) DI O,MAX
V OUT )
DI O,MAX
Dt
OUT,MIN
)
D ( L O,MIN
O,MIN
ESL
NB OUT,MIN
) determined above:
ESR
) and the number of
OUT,MIN
DV O,MAX
DI O,MAX
f SW ) ]
):
(eq. 1)
(eq. 2)
(eq. 3)