NCP5318FTR2G ON Semiconductor, NCP5318FTR2G Datasheet - Page 24

• Manufacturer Part Number: NCP5318FTR2G
• Description: IC CTLR CPU 2/3/4 PHASE 32-LQFP
• Manufacturer: ON Semiconductor

Specifications of NCP5318FTR2G

• Applications: Controller, CPU
• Voltage - Input: 9.5 ~ 13.2 V
• Number Of Outputs: 4
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Switching Frequency: 1 MHz
• Mounting Style: SMD/SMT
• Primary Input Voltage: 18V
• No. Of Pins: 32
• Operating Temperature Range: 0°C To +70°C
• Termination Type: SMD
• Supply Voltage Min: 12V
• Packaging Type: Tape And Reel
• Peak Reflow Compatible (260 C): Yes
• Frequency: 1MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP5318FTR2G; NCP5318FTR2GOSTR

capacitors must initially deliver most of the input current.
The amount of voltage drop across the input capacitors
(DV
capacitors (NB
current in the output inductor according to:
inductor (V
to the input voltage V
drop across the input capacitors, DV
input inductor as well. From this, the minimum value of the
input inductor can be calculated from:
dI
slew rate.
is relatively conservative. It assumes the supply voltage is
very “stiff” and does not account for any parasitic elements
that will limit dI/dt such as stray inductance. Also, the ESR
values of the capacitors specified by the manufacturer’s data
sheets are worst case high limits. In reality, input voltage
“sag,” lower capacitor ESRs and stray inductance will
further reduce the slew rate of the input current.
support the maximum current without saturating. Also, for
an inexpensive iron powder core, such as the −26 or −52
from Micrometals, the inductance “swing” with DC bias
must be taken into account since inductance will decrease as
the DC input current increases. At the maximum input
current, the inductance must not decrease below the
minimum value or the dI/dt will be higher than expected.
IN
Current changes slowly in the input inductor so the input
Before the load is applied, the voltage across the input
The input inductance value calculated from Equation 19
As with the output inductor, the input inductor must
/dt
CIN
MAX
) is determined by the number of bulk input
LIN
DV CIN + ESR IN
is the maximum allowable input current
) is very small and the input capacitors charge
IN
), their per capacitor ESR (ESR
+
−
IN
Li MIN
I
Li
Vi
12 V
. After the load is applied, the voltage
NB IN
470 nH
Li
+ V LIN
+ DV CIN
NB
(
(
dt MAX
ESR
dt MAX
dI IN
dI IN
IN
dl Lo
MAX dI/dt occurs in
first few PWM cycles.
Vi(t = 0) = 12 V
dt
× CB
IN
)
CIN
)
/NB
Figure 24. Calculating the Input Inductance
, appears across the
IN
IN
f SW
D
+
V
Ci
IN
) and the
Q1
(eq. 18)
(eq. 19)
http://onsemi.com
SWNODE
24
Q2
6. MOSFET and Heatsink Selection
drive MOSFET selection. To adequately size the heat sink,
the design must first predict the MOSFET power
dissipation. Once the dissipation is known, the heat sink
thermal impedance can be calculated to prevent the
specified maximum case or junction temperatures from
being exceeded at the highest ambient temperature. Power
dissipation has two primary contributors: conduction losses
and switching losses. The control or upper MOSFET will
display both switching and conduction losses. The
synchronous or lower MOSFET will exhibit only
conduction losses because it switches with nearly zero
voltage. However, the body diode in the synchronous
MOSFET will incur diode losses during the non−overlap
time of the gate drivers.
can be approximated from:
when the MOSFET is ON while the second term represents
switching OFF losses. The third term is the loss associated
with charging the control and synchronous MOSFET output
capacitances when the control MOSFET turns ON. The
output losses are caused by the output capacitances of both
the control and synchronous MOSFET but are dissipated
only in the control FET. The fourth term is the loss due to the
reverse recovered charge of the body diode in the
synchronous MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
P D,CONTROL + (I RMS,CNTL 2
Power dissipation, package size and thermal requirements
For the upper or control MOSFET, the power dissipation
The first term represents the conduction or I
I
Lo
) (I Lo,MAX
) (
Lo
Q oss
2
+
ESR
NB
Vo(t = 0) = 1.480 V
V IN
OUT
OUT
Q switch
× CB
/NB
I g
f SW ) ) (V IN @ Q RR @ f SW )
OUT
V
OUT
OUT
60 u(t)
V IN
R DS(on) )
f SW )
2
R losses
(eq. 20)