SC2544TSTRT Semtech, SC2544TSTRT Datasheet - Page 13

• Manufacturer Part Number: SC2544TSTRT
• Description: IC CTRL/REG SYNC BUCK 24-TSSOP
• Manufacturer: Semtech
• Type: Step-Down (Buck)r

Specifications of SC2544TSTRT

• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 2
• Voltage - Output: Adj to 0.75V
• Frequency - Switching: 100kHz ~ 300kHz
• Voltage - Input: 4.5 ~ 28 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Power - Output: -
• Other names: SC2544TSTR

Sometimes meeting tight input voltage ripple
specifications may require the use of larger input
capacitance. At full load, the peak-to-peak input
voltage ripple due to the ESR is
The peak-to-peak input voltage ripple due to the
capacitor is
From these two expressions, C
the input voltage ripple specification. In a multi-phase
converter, channel interleaving can be used to reduce
ripple. The two step-down channels of the SC2544
operate at 180 degrees from each other. If both step-
down channels in the SC2544 are connected to the
same input rail, the input RMS currents will be reduced.
Ripple cancellation effect of interleaving allows the
use of smaller input capacitors.
interleaved, the total DC input current is simply the
sum of the individual DC input currents. The combined
input current waveform depends on duty ratio and
the output current waveform. Assuming that the
output current ripple is small, the following formula
can be used to estimate the RMS value of the ripple
current in the input capacitor.
If D
Let the duty ratio and output current of Channel 1 and
Channel 2 be D
If D
If D
If D
I
POWER MANAGEMENT
I
I
Applications Information (Cont.)
Cin
Cin
Cin
When two channels with a common input are
2005 Semtech Corp.
1
1
1
1
>0.5 and D
<0.5 and D
>0.5 and (D
>0.5 and D
I
Cin
D (
. 0
. 0
I 5
I 5
1
o
o
1
1
2
2
D
D
2
1
I
o
D (
D
1
2
1
1
2
2
v
, D
2
1
2
v
I )(
I (
<0.5, then
1
C
ESR
> 0.5, then
o
-0.5) < D
< (D
D
1
o
2
0
1
2
5 .
I
and I
C
o
I
DI
o
I
2
I )(
o
in
1
2
2
R
2
-0.5) < 0.5, then
)
o
f
.
o
)
s
2
esr
1
2
,
o1
1 (
D (
, I
I
2
1 (
o
<0.5, then
2
o2
1
)
2
2
IN
, respectively.
D
)
D
. I
o
2
can be found to meet
D (
2
I )
o
2
1
2
0
5 .
D
1 (
I )
1
o
2
2
D
0
.
5 .
1
I )
I )
o
2
o
2
2
2
.
.
13
Choosing P
Choosing P
Choosing P
Choosing P
Choosing Po o o o o w w w w w er MOSFET
Main considerations in selecting the MOSFET’s are
power dissipation, MOSFETs cost, and packaging.
Switching losses and conduction losses of the MOSFET’s
are directly related to the total gate charge (C
channel on-resistance (R
performance of MOSFET’s, the product of the total
gate charge and on-resistance is used as a figure of
merit (FOM). Transistors with the same FOM follow
the same curve in Figure 8.
The closer the curve is to the origin, the lower is the
FOM. This means lower switching loss or lower
conduction loss or both. It may be difficult to find
MOSFET’s with both low C
trade-off between R
MOSFET selection also depends on applications. In
many applications, either switching loss or conduction
loss dominates for a particular MOSFET. For
synchronous buck converters with high input to output
voltage ratios, the top MOSFET is hard switched but
conducts with very low duty cycle. The bottom switch
conducts at high duty cycle but switches at near zero
voltage. For such applications, MOSFET’s with low C
are used for the top switch and MOSFET’s with low
R
MOSFET power dissipation consists of
a) conduction loss due to the channel resistance R
b) switching loss due to the switch rise time t
fall time t
c) the gate loss due to the gate resistance R
ds(on)
are used for the bottom switch.
Cg 100 Rds
Cg 200 Rds
Cg 500 Rds
(
(
(
Figure 8. Figure of Merit curves.
f
; and
,
,
,
50
er MOSFET
er MOSFET
er MOSFET
er MOSFETs s s s s
1
)
)
)
40
20
0
1
0
ds(on
FOM:100*10^{-12}
FOM:200*10^{-12}
FOM:500*10^{-12}
and C
ds(on)
On-resistance (mOhm)
5
g
and low R
). In order to judge the
g
Rds
10
has to be made.
www.semtech.com
ds(on
15
SC2544
. Usually a
G
20
20
.
g
) and
r
ds(on)
and
g
;