L6712ADTR STMicroelectronics, L6712ADTR Datasheet - Page 20

• Manufacturer Part Number: L6712ADTR
• Description: IC CTRLR DC/DC 2PH SYNC 28SOIC
• Manufacturer: STMicroelectronics
• Type: Step-Down (Buck)r

Specifications of L6712ADTR

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.9 ~ 3.3 V
• Current - Output: 2A
• Frequency - Switching: 150kHz
• Voltage - Input: 12V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Power - Output: 2W
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-4218-2

L6712A L6712
Figure 16. Main Control Loop Diagram
3.12.1Current Sharing (CS) Control Loop
Active current sharing is implemented using the information from Trans conductance differential amplifier.
A current reference equal to the average of the read current (I
read current and this reference is converted to a voltage with a proper gain and it is used to adjust the duty
cycle whose dominant value is set by the error amplifier at COMP pin (See Figure 17).
The current sharing control is a high bandwidth control loop allowing current sharing even during load transients.
The current sharing error is affected by the choice of external components; choose precise Rg resistor
(±1% is necessary) to sense the current. The current sharing error is internally dominated by the voltage
offset of Trans conductance differential amplifier; considering a voltage offset equal to 2mV across the
sense resistor, the current reading error is given by the following equation:
Figure 17. Current Sharing Control Loop.
20/29
COMP
D03IN1518
+
+
+
+
4/5
COMP
AMPLIFIER
PWM1
PWM2
ERROR
1/5
1/5
PWM1
PWM2
∆I
------------------- -
1/5
1/5
I
MAX
READ
Z
F(S)
+
-
D02IN1393
CORRECTION
DUTY CYCLE
=
CURRENT
SHARING
PROGRAMMED
CORRECTION
DUTY CYCLE
--------------------------------------- -
R
REFERENCE
CURRENT
SHARING
SENSE
BY VID
FB
2mV
R
⋅
FB
I
I
I
INFO2
INFO1
AVG
MAX
L 1
L 2
I
I
INFO2
INFO1
) is internally built; the error between the
C
RA_Gain
L 1
L 2
O
V
OUT
R
O