LTC1735CS-1 Linear Technology, LTC1735CS-1 Datasheet - Page 21

• Manufacturer Part Number: LTC1735CS-1
• Description: IC REG SW SYNC STEPDWN HE 16SOIC
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC1735CS-1

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.8 ~ 6 V
• Current - Output: 3A
• Frequency - Switching: 300kHz
• Voltage - Input: 4 ~ 30 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

APPLICATIO S I FOR ATIO
decreases the output voltage starts at a level lower than
nominal so the output voltage can have more overshoot
and stay within the specified voltage range. Less output
capacitance is required when voltage positioning is used
because more voltage variation is allowed on the output
capacitors.
Active voltage positioning can be implemented using the
OPTI-LOOP architecture of the LTC1735-1 and two resis-
tors connected to the I
introduced when the error amplifier has to drive a resistive
load. This offset voltage is limited to 30mV at the input
of the error amplifier. The resulting change in output
voltage is the product of input offset voltage and the
feedback voltage divider ratio.
Figure 8 shows a CPU-core-voltage regulator with active
voltage positioning. Resistors R1 and R5 force the input
voltage offset that adjusts the output voltage according to
the load current level. To select values for R1 and R5, first
determine the amount of output deregulation allowed. The
actual specification for a typical microprocessor allows
the output to vary 0.112V. The LTC1735-1 reference
100pF
0.1 F
47pF
C6
C2
C4
100k
27k
R1
R2
PGOOD
100pF
39pF
C1
C3
1000pF
C5
U
1
2
3
4
5
6
7
8
C
RUN/SS
I
PGOOD
SENSE
SENSE
V
SGND
TH
TH
OSC
OSENSE
LTC1735-1
U
R3 680k
R4 100k
R5 100k
pin. An input voltage offset is
–
+
U1
Figure 8. CPU-Core-Voltage Regulator with Active Voltage Positioning
EXTV
INTV
BOOST
PGND
SW
V
TG
BG
CC
CC
IN
W
16
15
14
13
12
11
10
9
5V (OPTIONAL)
D1
CMDSH-3
C9
1 F
U
+
C8
0.22 F
C7
0.1 F
C10
4.7 F
10V
Q1
FDS6680A
MBRS340
Q2, Q3
FDS6680A
accuracy is 1%. Using 1% tolerance resistors, the total
feedback divider accuracy is about 1% because both
feedback resistors are close to the same value. The result-
ing setpoint accuracy is 2% so the output transient
voltage cannot exceed 0.082V. For V
maximum output voltage change controlled by the I
would be:
With optimum resistor values at the I
voltage will swing from 1.55V at minimum load to 1.44V
at full load. At this output voltage, active voltage position-
ing provides an additional 56mV to the allowable tran-
sient voltage on the output capacitors, a 68% improvement
over the
positioning.
2
D2
V
OSENSE
C9, C19: TAIYO YUDEN JMK107BJ105
C10: KEMET T494A475M010AS
C12 TO C14: TAIYO YUDEN GMK325F106
C15 TO C18: PANASONIC EEFUE0G181R
D1: CENTRAL SEMI CMDSH-3
D2: MOTOROLA MBRS340
L1: PANASONIC ETQP6F1R0SA
Q1 TO Q3: FAIRCHILD FDS6680A
R5: IRC LRF2512-01-R003-J
U1: LINEAR TECHNOLOGY LTC1735CS-1
1 H
L1
82mV allowed without active voltage
Input Offset Voltage V
0.003
0 03
R6
.
0 8
.
V
V
• .
1735-1 F08
1 5
C11
330pF
V
11.5k
10k
REF
R7
R8
+
56
LTC1735-1
mV
•
C15 TO
C18
180 F
4V
TH
OUT
OUT
C12 TO C14
10 F
35V
pin, the output
= 1.5V, the
C19
1 F
21
TH
V
7.5V TO
24V
GND
V
1.5V
15A
GND
IN
OUT
pin