LT1371CR Linear Technology, LT1371CR Datasheet - Page 11

• Manufacturer Part Number: LT1371CR
• Description: IC SWTCHNG REG 3A HI-EFF 7-DD
• Manufacturer: Linear Technology
• Type: Step-Down (Buck), Step-Up (Boost), Inverting, Cuk, Flyback, Forward Converterr

Specifications of LT1371CR

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1.25 ~ 35 V
• Current - Output: 3A
• Frequency - Switching: 500kHz
• Voltage - Input: 2.7 ~ 25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: D²Pak, TO-263 (7 leads + tab)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

APPLICATIO S I FOR ATIO
maximum output load current and will also be increased if
poor quality (high ESR) output capacitors are used. The
addition of a 0.0047 F capacitor on the V
switching frequency ripple to only a few millivolts. A low
value for R
margin may be inadequate.
Layout Considerations
For maximum efficiency, LT1371 switch rise and fall times
are made as short as possible. To prevent radiation and
high frequency resonance problems, proper layout of the
components connected to the switch node is essential. B
field (magnetic) radiation is minimized by keeping output
diode, Switch pin and output bypass capacitor leads as
short as possible. Figures 3, 4 and 5 show recommended
positions for these components. E field radiation is kept
low by minimizing the length and area of all traces con-
nected to the Switch pin. A ground plane should always be
used under the switcher circuitry to prevent interplane
coupling.
The high speed switching current path is shown schemati-
cally in Figure 6. Minimum lead length in this path is
essential to ensure clean switching and low EMI. The path
including the switch, output diode and output capacitor is
the only one containing nanosecond rise and fall times.
Keep this path as short as possible.
AND TAB DIRECTLY
TO GROUND PLANE
GROUND PIN
CONNECT
Figure 3. Layout Considerations— R Package
C
will also reduce V
V
C
FB
U U
NFB
GND
V
SW
S/S
V
C
D
IN
pin ripple, but loop phase
C
W
C
KEEP PATH FROM
V
OUTPUT CAPACITORS
AND GROUND RETURN
AS SHORT AS POSSIBLE
SW
C
, OUTPUT DIODE,
pin reduces
U
LT1371 • F03
TO GROUND PLANE.
*SEE T7 PACKAGE LAYOUT CONSIDERATIONS FOR VERTICAL MOUNTING
AND TAB DIRECTLY
V
OF THE T7 PACKAGE
GROUND PLANE*
IN
CONNECT ALL GROUND PINS TO GROUND PLANE
SOLDERED OR
GROUND PIN
TAB MAY BE
BOLTED TO
CONNECT
Figure 5. Layout Considerations— SW Package
V
FB
NFB
GND
GND
GND
GND
SHDN
SYNC
V
Figure 4. Layout Considerations— T7 Package
C
IN
L1
V
SWITCH
C
NODE
FB
GND
GND
GND
GND
GND
V
V
SW
SW
NC
NC
NC
NFB
GND
CIRCULATING
V
FREQUENCY
Figure 6
SW
PATH
HIGH
S/S
V
D
C
C
D
IN
C
KEEP PATH FROM
V
OUTPUT CAPACITORS
AND GROUND RETURN
AS SHORT AS POSSIBLE
C
KEEP PATH FROM
V
OUTPUT CAPACITORS
AND GROUND RETURN
AS SHORT AS POSSIBLE
SW
SW
, OUTPUT DIODE,
, OUTPUT DIODE,
LT1371
LOAD
11
LT1371 • F06
LT1371 • F05
V
OUT
LT1371 • F04