KSZ8695PX Micrel Inc, KSZ8695PX Datasheet - Page 30

• Manufacturer Part Number: KSZ8695PX
• Description: IC SWITCH 10/100 1PORT 289PBGA
• Manufacturer: Micrel Inc

Specifications of KSZ8695PX

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 289-PBGA
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: KSZ8695PX-EVAL - EVAL KIT EXPERIMENT ONLY KSZ8695
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1024

Factory Test Pins
Note:
1. I = Input.
September 2005
KS8695PX
O = Output.
O/I = Output in normal mode; input pin during reset.
M17
M17
M17
M17
M17
T17
T17
T17
T17
T17
N17
N17
N17
N17
N17
P17
P17
P17
P17
P17
R17
R17
R17
R17
R17
E15
E15
E15
E15
E15
E14
E14
E14
E14
E14
Pin
Pin
Pin
Pin
Pin
Pin
Pin
M4
M4
M4
M4
M4
F7
F7
F7
F7
F7
F4
F4
F4
F4
F4
TICTESTENN
TICTESTENN
TICTESTENN
TICTESTENN
TICTESTENN
TESTREQB
TESTREQB
TESTREQB
TESTREQB
TESTREQB
TESTREQA
TESTREQA
TESTREQA
TESTREQA
TESTREQA
WRSTPLS
WRSTPLS
WRSTPLS
WRSTPLS
WRSTPLS
ERWEN0/
ERWEN0/
ERWEN0/
ERWEN0/
ERWEN0/
TESTACK
TESTACK
TESTACK
TESTACK
TESTACK
ERWEN1/
ERWEN1/
ERWEN1/
ERWEN1/
ERWEN1/
ERWEN2/
ERWEN2/
ERWEN2/
ERWEN2/
ERWEN2/
ERWEN3/
ERWEN3/
ERWEN3/
ERWEN3/
ERWEN3/
B0SIZE0
B0SIZE0
B0SIZE0
B0SIZE0
B0SIZE0
B0SIZE1
B0SIZE1
B0SIZE1
B0SIZE1
B0SIZE1
TESTEN
TESTEN
TESTEN
TESTEN
TESTEN
EROEN/
EROEN/
EROEN/
EROEN/
EROEN/
WLED0/
WLED0/
WLED0/
WLED0/
WLED0/
WLED1/
WLED1/
WLED1/
WLED1/
WLED1/
TEST1
TEST1
TEST1
TEST1
TEST1
TEST2
TEST2
TEST2
TEST2
TEST2
Name
Name
Name
Name
Name
Name
Name
I/O Type
I/O Type
I/O Type
I/O Type
I/O Type
I/O Type
I/O Type
O/I
O/I
O/I
O/I
O/I
O/I
O/I
O/I
O/I
O/I
O/I
O/I
O/I
O/I
O/I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
(1)
(1)
Description
Description
Normal mode: External I/O and ROM/SRAM/FLASH output enable: Active low.
Normal mode: External I/O and ROM/SRAM/FLASH output enable: Active low.
Normal mode: External I/O and ROM/SRAM/FLASH output enable: Active low.
Normal mode: External I/O and ROM/SRAM/FLASH output enable: Active low.
Normal mode: External I/O and ROM/SRAM/FLASH output enable: Active low.
When asserted, this signal controls the output enable port of the specifi ed memory
When asserted, this signal controls the output enable port of the specifi ed memory
When asserted, this signal controls the output enable port of the specifi ed memory
When asserted, this signal controls the output enable port of the specifi ed memory
When asserted, this signal controls the output enable port of the specifi ed memory
device.
device.
device.
device.
device.
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, active low;
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, active low;
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, active low;
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, active low;
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, active low;
WRSTPLS = 1, active high. No default.
WRSTPLS = 1, active high. No default.
WRSTPLS = 1, active high. No default.
WRSTPLS = 1, active high. No default.
WRSTPLS = 1, active high. No default.
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
the ERWENx controls the byte write enable of the memory device (except SDRAM).
the ERWENx controls the byte write enable of the memory device (except SDRAM).
the ERWENx controls the byte write enable of the memory device (except SDRAM).
the ERWENx controls the byte write enable of the memory device (except SDRAM).
the ERWENx controls the byte write enable of the memory device (except SDRAM).
ARM CPU test signal (factory reserved test signal).
ARM CPU test signal (factory reserved test signal).
ARM CPU test signal (factory reserved test signal).
ARM CPU test signal (factory reserved test signal).
ARM CPU test signal (factory reserved test signal).
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
the ERWENx controls the byte write enable of the memory device (except SDRAM).
the ERWENx controls the byte write enable of the memory device (except SDRAM).
the ERWENx controls the byte write enable of the memory device (except SDRAM).
the ERWENx controls the byte write enable of the memory device (except SDRAM).
the ERWENx controls the byte write enable of the memory device (except SDRAM).
ARM CPU test signal (factory reserved test signal).
ARM CPU test signal (factory reserved test signal).
ARM CPU test signal (factory reserved test signal).
ARM CPU test signal (factory reserved test signal).
ARM CPU test signal (factory reserved test signal).
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
the ERWENx controls the byte write enable of the memory device except SDRAM).
the ERWENx controls the byte write enable of the memory device except SDRAM).
the ERWENx controls the byte write enable of the memory device except SDRAM).
the ERWENx controls the byte write enable of the memory device except SDRAM).
the ERWENx controls the byte write enable of the memory device except SDRAM).
ARM CPU test signal (factory reserved test signal).
ARM CPU test signal (factory reserved test signal).
ARM CPU test signal (factory reserved test signal).
ARM CPU test signal (factory reserved test signal).
ARM CPU test signal (factory reserved test signal).
External I/O and ROM/SRAM/FLASH write byte enable. Active low. When asserted,
External I/O and ROM/SRAM/FLASH write byte enable. Active low. When asserted,
External I/O and ROM/SRAM/FLASH write byte enable. Active low. When asserted,
External I/O and ROM/SRAM/FLASH write byte enable. Active low. When asserted,
External I/O and ROM/SRAM/FLASH write byte enable. Active low. When asserted,
the ERWENx controls the byte write enable of the memory device (except SDRAM).
the ERWENx controls the byte write enable of the memory device (except SDRAM).
the ERWENx controls the byte write enable of the memory device (except SDRAM).
the ERWENx controls the byte write enable of the memory device (except SDRAM).
the ERWENx controls the byte write enable of the memory device (except SDRAM).
ARM CPU test signal (factory reserved test signal).
ARM CPU test signal (factory reserved test signal).
ARM CPU test signal (factory reserved test signal).
ARM CPU test signal (factory reserved test signal).
ARM CPU test signal (factory reserved test signal).
Normal mode: WAN LED indicator 0: Programmable via WAN misc. Control register
Normal mode: WAN LED indicator 0: Programmable via WAN misc. Control register
Normal mode: WAN LED indicator 0: Programmable via WAN misc. Control register
Normal mode: WAN LED indicator 0: Programmable via WAN misc. Control register
Normal mode: WAN LED indicator 0: Programmable via WAN misc. Control register
bits [2:0].
bits [2:0].
bits [2:0].
bits [2:0].
bits [2:0].
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
B0SiZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
B0SiZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
B0SiZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
B0SiZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
B0SiZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
Normal mode: WAN LED indicator 1: Programmable via WAN Misc. Control register
Normal mode: WAN LED indicator 1: Programmable via WAN Misc. Control register
Normal mode: WAN LED indicator 1: Programmable via WAN Misc. Control register
Normal mode: WAN LED indicator 1: Programmable via WAN Misc. Control register
Normal mode: WAN LED indicator 1: Programmable via WAN Misc. Control register
bits [6:4].
bits [6:4].
bits [6:4].
bits [6:4].
bits [6:4].
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
B0SIZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
B0SIZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
B0SIZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
B0SIZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
B0SIZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
Description
Description
Factory test signal. Pull-down or direct connect to GND required.
Factory test signal. Pull-down or direct connect to GND required.
Factory test signal. Pull-down or direct connect to GND required.
Factory test signal. Pull-down or direct connect to GND required.
Factory test signal. Pull-down or direct connect to GND required.
Factory test signal. No connect for normal operation.
Factory test signal. No connect for normal operation.
Factory test signal. No connect for normal operation.
Factory test signal. No connect for normal operation.
Factory test signal. No connect for normal operation.
Factory test signal. No connect for normal operation.
Factory test signal. No connect for normal operation.
Factory test signal. No connect for normal operation.
Factory test signal. No connect for normal operation.
Factory test signal. No connect for normal operation.
30
M9999-091605
Micrel