AD9267BCPZ Analog Devices Inc, AD9267BCPZ Datasheet - Page 15

• Manufacturer Part Number: AD9267BCPZ
• Description: IC MOD SIGMA-DELTA DUAL 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9267BCPZ

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Resolution (bits): 16bit
• Sampling Rate: 640MSPS
• Input Channel Type: Differential
• Data Interface: Serial, SPI
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The second mode bypasses the clock multiplier circuitry and
allows the clock to be directly sourced. This mode enables the
user to source a very high quality clock directly to the Σ-Δ
modulator. Sourcing the clock directly may be necessary in
demanding applications that require the lowest possible output
noise. Refer to Figure 18, which shows the degradation in SNR
performance for the various PLL settings.
In either case, when using the on-chip clock multiplier or
sourcing the high speed clock directly, it is necessary that the
clock source have low jitter to maximize the Σ-Δ modulator
noise performance. High speed, high resolution ADCs and
modulators are sensitive to the quality of the clock input. As
jitter increases, the SNR performance of the AD9267 degrades
from that specified in Table 2. The jitter inherent to the part due
to the PLL root sum squares with any external clock jitter,
thereby degrading performance. To prevent jitter from dominating
the performance of the AD9267, the input clock source should be
no greater than 1 ps rms of jitter.
The CLK± inputs are self-biased to 450 mV (see Figure 21); if
dc-coupled, it is important to maintain the specified 450 mV
input common-mode voltage. Each input pin can safely swing
from 200 mV p-p to 1 V p-p single-ended about the 450 mV
common-mode voltage. The recommended clock inputs are
CMOS or LVPECL.
The specified clock rate of the Σ-Δ modulator, f
The clock rate possesses a direct relationship with the available
input bandwidth of the ADC.
In either case, using the on-chip clock multiplier to generate the
Σ-Δ modulator clock rate or directly sourcing the clock, any
deviation from 640 MHz results in a change in input bandwidth.
The input range of the clock is limited to 640 MHz ± 5%.
Direct Clocking
The default configuration of the AD9267 is for direct clocking
where the PLL is bypassed. Figure 38 shows one preferred
method for clocking the AD9267. A low jitter clock source is
converted from a single-ended signal to a differential signal
using an RF transformer. The back-to-back Schottky diodes
across the secondary side of the transformer limits clock
excursions into the AD9267 to approximately 0.8 V p-p differen-
tial. This helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9267 while
preserving the fast rise and fall times of the signal, which are
critical to achieving low jitter.
CLOCK
INPUT
Bandwidth = f
Figure 38. Transformer-Coupled Differential Clock
50Ω
0.1µF
MOD
TC1-1-13M+, 1:1
MINI-CIRCUITS
÷ 64
XFMR
0.1µF
0.1µF
0.1µF
SCHOTTKY
HSM2812
DIODES:
CLK+
CLK–
MOD
, is 640 MHz.
AD9267
ADC
Rev. 0 | Page 15 of 24
If a differential clock is not available, the AD9267 can be driven
by a single-ended signal into the CLK+ terminal with the CLK−
terminal ac-coupled to ground. Figure 39 shows the circuit
configuration.
Another option is to ac couple a differential LVPECL signal to
the sample clock input pins, as shown in Figure 40. The AD951x
family of clock drivers is recommended because it offers excellent
jitter performance.
Internal PLL Clock Distribution
The alternative clocking option available on the AD9267 is to
apply a low frequency reference clock and use the on-chip clock
multiplier to generate the high frequency f
clock architecture is shown in Figure 41.
The clock multiplication circuit operates such that the VCO
outputs a frequency, f
multiplied by N
where N is the PLL multiplication (PLLMULT) factor.
The Σ-Δ modulator clock frequency, f
CLOCK
CLOCK
1
INPUT
INPUT
50Ω RESISTORS ARE OPTIONAL.
CLK±
f
f
CLOCK
VCO
MOD
INPUT
= (CLK±) × (N)
50Ω
= f
VCO
1
Figure 40. Differential LVPECL Sample Clock
50Ω
0.1µF
0.1µF
÷ 2
DETECTOR
Figure 41. Internal Clock Architecture
50Ω
1
PHASE
Figure 39. Single-Ended Clock
CLK
CLK
VCO
LVPECL
DRIVER
AD951x
0.1µF
PLLMULT
DIVIDER
0x0A[5:0]
, equal to the reference clock input
÷N
0.1µF
240Ω
FILTER
LOOP
SCHOTTKY
HSM2812
DIODES:
240Ω
MOD
PLL
÷2
100Ω
PLLENABLE
CLK+
CLK–
, is equal to
0.1µF
0.1µF
MOD
0x09[2]
VCO
CLK+
CLK–
rate. The internal
AD9267
ADC
MODULATOR
640MSPS
CLOCK
AD9267
AD9267
ADC