IDT89HPES48T12ZABR IDT, Integrated Device Technology Inc, IDT89HPES48T12ZABR Datasheet - Page 2

• Manufacturer Part Number: IDT89HPES48T12ZABR
• Description: IC PCI SW 48LANE 12PORT 1156BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES48T12ZABR

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: FCBGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES48T12ZABR

Product Description
the most efficient connectivity solution for applications requiring high
throughput, low latency, and simple board layout with a minimum
number of board layers. It provides 192 Gbps of aggregated switching
capacity through 48 integrated serial lanes, using proven and robust IDT
technology. Each lane provides 2.5 Gbps of bandwidth in both directions
and is fully compliant with PCI Express Base specification 1.1.
IDT 89PES48T12 Data Sheet
Utilizing standard PCI Express interconnect, the PES48T12 provides
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Power Management
Testability and Debug Features
32 General Purpose Input/Output pins
– Supports Hot-Swap
– Supports PCI Power Management Interface specification,
– Unused SerDes disabled
– Supports Advanced Configuration and Power Interface Speci-
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Packaged in a 35mm x 35mm 1156-ball Flip Chip BGA with
1mm ball spacing
• Compatible with Hot-Plug I/O expanders used on PC
• Supports powerdown modes not only at the link level (L0,
Note: The configurations in the above diagram show the maximum port widths. The PES48T12 can negotiate to narrower port widths — x4,
x2, or x1.
Revision 1.1 (PCI-PM)
fication, Revision 2.0 (ACPI) supporting active link state
motherboards
L0s, L1, L2/L3 Ready and L3) but also at the device level
(D0, D1, etc.)
x8
2
3
4 5
x8
Non-bifurcated
1 0
6 7
x8
x8
8 9
x8
Figure 2 Configuration Options
11
10
x8
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ture. The PCI Express layers consist of SerDes, Physical, Data Link and
Transaction layers. The PES48T12 can operate either as a store and
forward switch or a cut-through switch and is designed to switch memory
and I/O transactions. It supports eight Traffic Classes (TCs) and one
Virtual Channel (VC) with sophisticated resource management to enable
efficient switching and I/O connectivity.
x4
x4
x4
The PES48T12 is based on a flexible and efficient layered architec-
1
2
3
4
x4
Fully Bifurcated
5
x4
6
x4
0
x4
7
x4
8
x4
9
x4
11
10
December 21, 2006
x4
x4