IDT89HPES48T12ZABR IDT, Integrated Device Technology Inc, IDT89HPES48T12ZABR Datasheet - Page 9

• Manufacturer Part Number: IDT89HPES48T12ZABR
• Description: IC PCI SW 48LANE 12PORT 1156BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES48T12ZABR

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: FCBGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES48T12ZABR

IDT 89PES48T12 Data Sheet
P1011MERGEN
MSMBSMODE
SWMODE[3:0]
P01MERGEN
P23MERGEN
P45MERGEN
P67MERGEN
P89MERGEN
RSTHALT
Signal
CCLKDS
CCLKUS
PERSTN
Type
I
I
I
I
I
I
I
I
I
I
I
I
Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a
common clock is being used between the downstream device and the downstream
port.
Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a
common clock is being used between the upstream device and the upstream port.
Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus
should operate at 100 KHz instead of 400 KHz. This value may not be overridden.
Port 0 and 1 Merge. When this pin is asserted, port 1 is merged with port 0 to form a
single x8 port. The SerDes lanes associated with port 1 become lanes 4 through 7 of
port 0.
Port 2 and 3 Merge. When this pin is asserted, port 3 is merged with port 2 to form a
single x8 port. The SerDes lanes associated with port 3 become lanes 4 through 7 of
port 2.
Port 4 and 5 Merge. When this pin is asserted, port 5 is merged with port 4 to form a
single x8 port. The SerDes lanes associated with port 5 become lanes 4 through 7 of
port 4.
Port 6 and 7 Merge. When this pin is asserted, port 7 is merged with port 6 to form a
single x8 port. The SerDes lanes associated with port 7 become lanes 4 through 7 of
port 6.
Port 8 and 9 Merge. When this pin is asserted, port 9 is merged with port 8 to form a
single x8 port. The SerDes lanes associated with port 9 become lanes 4 through 7 of
port 8.
Port 10 and 11 Merge. When this pin is asserted, port 11 is merged with port 10 to
form a single x8 port. The SerDes lanes associated with port 11 become lanes 4
through 7 of port 10.
Fundamental Reset. Assertion of this signal resets all logic inside the PES48T12 and
initiates a PCI Express fundamental reset.
Reset Halt. When this signal is asserted during a PCI Express fundamental reset,
PES48T12 executes the reset procedure and remains in a reset state with the Master
and Slave SMBuses active. This allows software to read and write registers internal to
the device before normal device operation begins. The device exits the reset state
when the RSTHALT bit is cleared in the PA_SWCTL register by an SMBus master.
Switch Mode. These configuration pins determine the PES48T12 switch operating
mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - Normal switch mode with upstream port failover (port 0 selected as the
0x9 - Normal switch mode with upstream port failover (port 2 selected as the
0xA - Normal switch mode with Serial EEPROM initialization and upstream port
0xB - Normal switch mode with Serial EEPROM initialization and upstream port
0xC through 0xF - Reserved
upstream port)
upstream port)
failover (port 0 selected as the upstream port)
failover (port 2 selected as the upstream port)
Table 5 System Pins
9 of 46
Name/Description
December 21, 2006