KS8842-32MQL Micrel Inc, KS8842-32MQL Datasheet - Page 118

• Manufacturer Part Number: KS8842-32MQL
• Description: IC SWITCH 10/100 32BIT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8842-32MQL

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: KS8842-PMQL-EVAL - EVAL KIT EXPERIMENTAL KS8842KS8842-16MQL-EVAL - EVAL KIT EXPERIMENTAL KS8842
• Lead Free Status / RoHS Status: Not Compliant, Lead free / RoHS Compliant
• Other names: 576-1459

Examples:
Additional MIB Information
Per Port MIB counters are designed as “read clear”. That is, these counters will be cleared after they are read.
All Ports Dropped Packet MIB counters are not cleared after they are accessed. The application needs to keep track of
overflow and valid conditions on these counters.
Micrel, Inc.
October 2007
1. MIB Counter Read (read port 1 “Rx64Octets” counter at indirect address offset 0x0E)
Then
2. MIB Counter Read (read port 2 “Rx64Octets” counter at indirect address offset 0x2E)
Then
3. MIB Counter Read (read “Port1 TX Drop Packets” counter at indirect address offset 0x100)
Then
Write to reg. IACR with 0x1c0e (set indirect address and trigger a read MIB counters operation)
Read reg. IADR5 (MIB counter value 31-16) // If bit 31 = 1, there was a counter overflow
Read reg. IADR4 (MIB counter value 15-0)
Write to reg. IACR with 0x1c2e (set indirect address and trigger a read MIB counters operation)
Read reg. IADR5 (MIB counter value 31-16) // If bit 31 = 1, there was a counter overflow
Read reg. IADR4 (MIB counter value 15-0)
Write to reg. IACR with 0x1d00 (set indirect address and trigger a read MIB counters operation)
Read reg. IADR4 (MIB counter value 15-0)
118
// If bit 30 = 0, restart (reread) from this register
// If bit 30 = 0, restart (reread) from this register
KSZ8842-16/32 MQL/MVL/MVLI/MBL
M9999-102207-1.9