KS8842-32MQL Micrel Inc, KS8842-32MQL Datasheet - Page 5

• Manufacturer Part Number: KS8842-32MQL
• Description: IC SWITCH 10/100 32BIT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8842-32MQL

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: KS8842-PMQL-EVAL - EVAL KIT EXPERIMENTAL KS8842KS8842-16MQL-EVAL - EVAL KIT EXPERIMENTAL KS8842
• Lead Free Status / RoHS Status: Not Compliant, Lead free / RoHS Compliant
• Other names: 576-1459

CPU Interface I/O Registers .................................................................................................................................. 51
Register Map: Switch & MAC/PHY ....................................................................................................................... 60
Micrel, Inc.
October 2007
IPv6 MLD Snooping...............................................................................................................................................................45
Port Mirroring Support ...........................................................................................................................................................45
IEEE 802.1Q VLAN Support..................................................................................................................................................45
QoS Priority Support..............................................................................................................................................................46
Port-Based Priority.................................................................................................................................................................46
802.1p-Based Priority ............................................................................................................................................................46
DiffServ based Priority ...........................................................................................................................................................47
Rate Limiting Support ............................................................................................................................................................47
MAC Filtering Function ..........................................................................................................................................................48
Configuration Interface ..........................................................................................................................................................48
EEPROM Interface ................................................................................................................................................................48
Loopback Support .................................................................................................................................................................49
I/O Registers..........................................................................................................................................................................51
Internal I/O Space Mapping ...................................................................................................................................................52
Bit Type Definition .................................................................................................................................................................60
Bank 0-63 Bank Select Register (0x0E): BSR (same location in all Banks) ..........................................................................60
Bank 0 Base Address Register (0x00): BAR .........................................................................................................................60
Bank 0 QMU RX Flow Control High Watermark Configuration Register (0x04): QRFCR ......................................................61
Bank 0 Bus Error Status Register (0x06): BESR ...................................................................................................................61
Bank 0 Bus Burst Length Register (0x08): BBLR ..................................................................................................................61
Bank 1: Reserved ..................................................................................................................................................................62
Bank 2 Host MAC Address Register Low (0x00): MARL .......................................................................................................62
Bank 2 Host MAC Address Register Middle (0x02): MARM ..................................................................................................62
Bank 2 Host MAC Address Register High (0x04): MARH......................................................................................................62
Bank 3 On-Chip Bus Control Register (0x00): OBCR............................................................................................................63
Bank 3 EEPROM Control Register (0x02): EEPCR...............................................................................................................63
Bank 3 Memory BIST INFO Register (0x04): MBIR...............................................................................................................64
Bank 3 Global Reset Register (0x06): GRR ..........................................................................................................................64
Bank 3 Bus Configuration Register (0x08): BCFG.................................................................................................................64
Banks 4 – 15: Reserved ........................................................................................................................................................64
Bank 16 Transmit Control Register (0x00): TXCR .................................................................................................................65
Bank 16 Transmit Status Register (0x02): TXSR ..................................................................................................................65
Bank 16 Receive Control Register (0x04): RXCR .................................................................................................................65
Bank 16 TXQ Memory Information Register (0x08): TXMIR..................................................................................................66
Bank 16 RXQ Memory Information Register (0x0A): RXMIR.................................................................................................66
Bank 17 TXQ Command Register (0x00): TXQCR................................................................................................................67
Bank 17 RXQ Command Register (0x02): RXQCR ...............................................................................................................67
Bank 17 TX Frame Data Pointer Register (0x04): TXFDPR ..................................................................................................67
Bank 17 RX Frame Data Pointer Register (0x06): RXFDPR .................................................................................................68
Bank 17 QMU Data Register Low (0x08): QDRL...................................................................................................................68
Bank 17 QMU Data Register High (0x0A): QDRH .................................................................................................................68
Bank 18 Interrupt Enable Register (0x00): IER......................................................................................................................69
Bank 18 Interrupt Status Register (0x02): ISR.......................................................................................................................70
Bank 18 Receive Status Register (0x04): RXSR ...................................................................................................................71
Bank 18 Receive Byte Counter Register (0x06): RXBC ........................................................................................................72
Bank 19 Multicast Table Register 0 (0x00): MTR0 ................................................................................................................72
Bank 19 Multicast Table Register 1 (0x02): MTR1 ................................................................................................................72
Bank 19 Multicast Table Register 2 (0x04): MTR2 ................................................................................................................72
“Multicast Address Insertion” in the Static MAC Table ......................................................................................................45
Far-end Loopback.............................................................................................................................................................49
Near-end (Remote) Loopback ..........................................................................................................................................49
5
KSZ8842-16/32 MQL/MVL/MVLI/MBL
M9999-102207-1.9