CY7C9235A-270JXC Cypress Semiconductor Corp, CY7C9235A-270JXC Datasheet - Page 2

• Manufacturer Part Number: CY7C9235A-270JXC
• Description: IC SMPTE ENCODER 44-PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9235A-270JXC

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-02082 Rev. **
Pin Configuration
Pin Descriptions
ENA
ENN
BYPASS
TRS_DET
TRS_FILT
SVS_EN
Name
Input
Input
Input
Output
Input
Input
I/O
CY7C9235A SMPTE-259M Encoder
TRS_FILT
TRS_DET
PD
Enable Parallel Data. If ENA is LOW at the rising edge of CKW, the data present on the PD
is latched, and routed to the Q
If the CY7C9235A is only used in SMPTE-259M mode this signal should be tied to V
Enable Next Parallel Data. If ENN is LOW at the rising edge of CKW, the data present on the PD
inputs at the next rising edge of TXCLK is latched, and routed to the Q
interpreted when DVB_EN is active (LOW). If the CY7C9235A is only used in SMPTE-259M mode
this signal should be tied to V
Bypass SMPTE Encoding. BYPASS is ignored if DVB_EN is active (LOW). If BYPASS is HIGH at
the rising edge of CKW (and DVB_EN is HIGH), the data latched into the input register is routed
around both the SMPTE scrambler and the NRZI encoder and presented to the output register. If
BYPASS is LOW at the rising edge of the CKW clock (and DVB_EN is HIGH), the data present in
the input register is routed through the SMPTE scrambler and NRZI encoder.
TRS Character Detected. This output indicates when a character used in the TRS sequence is
detected in the input register. If the data contains any of the reserved characters of 000–003 or
3FC–3FF in 10-bit hex, the output will be LOW for one clock period. If the character in the input
register is any other pattern (or DVB_EN is LOW) this output will remain HIGH.
TRS Character Filter. This signal controls an internal filter that converts the low-order two bits of all
TRS characters to same state as the upper eight bits. This allows a proper 30-bit TRS ID to be
generated when the CY7C9235A is operated with 8-bit or non-standard video streams. When this
signal is LOW, all characters from 000–003 are converted to 000, and all characters from 3FC–3FF
are converted to 3FF. When TRS_FILT is disabled (HIGH), all characters are passed to the scrambler
without modification. This signal has no effect when DVB_EN is active (LOW).
Send Violation Symbol Enable. This input is only valid when DVB_EN is active (LOW). If SVS_EN
is HIGH and a HIGH input is present on PD
the CY7B9234 serializer to generate an invalid 8B/10B character. If SVS_EN is LOW, the level
present on PD
DVB_EN
BYPASS
SVS_EN
9
(SVS)
V
V
V
NC
OE
SS
SS
SS
10
11
12
13
14
15
16
17
7
8
9
9
is ignored and Q
18
6
19
5
NC
20
4
0–9
21
SS
3
.
Top View
outputs. This pin is only interpreted when DVB_EN is active (LOW).
9
22
is forced to a LOW state.
2
PLCC
23
1
44
24
9
Description
, Q
9
43
25
will also be high on a following clock cycle, forcing
42
26
41
27
40
28
39
38
37
36
35
34
33
32
31
30
29
Q
ENA_OUT
ENN
ENA
V
V
SC/D_EN
NC
NC
CKW
V
0–9
SS
SS
SS
0
(SC/D)
outputs. This pin is only
CY7C9235A
SS
.
Page 2 of 8
0 9
inputs
0–9