MT16VDDF12864HG-335D2 Micron Technology Inc, MT16VDDF12864HG-335D2 Datasheet - Page 14
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MT16VDDF12864HG-335D2
Manufacturer Part Number
MT16VDDF12864HG-335D2
Description
MODULE DDR SDRAM 1GB 200-SODIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT16VDDF12864HY-335F2.pdf
(30 pages)
Specifications of MT16VDDF12864HG-335D2
Memory Type
DDR SDRAM
Memory Size
1GB
Speed
167MHz
Package / Case
200-SODIMM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1109
Table 12: I
Notes: 1–5, 8, 10, 12, 47; DDR SDRAM devices only; notes appear on pages 18–21; 0°C
pdf: 09005aef80a77a90, source: 09005aef80a646bc
DDF16C64_128x64HG.fm - Rev. D 9/04 EN
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge;
t
per clock cycle; Address and control inputs changing once every
two clock cycles
OPERATING CURRENT: One device bank; Active-Read-
Precharge; Burst = 4;
0mA; Address and control inputs
PRECHARGE POWER-DOWN STANDBY CURRENT: All device
banks idle; Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle;
t
changing once per clock
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode;
CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
device bank active
DQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2;
device bank active; Address and control inputs changing once per
clock cycle;
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank
clock cycle;
twice per clock cycle
AUTO REFRESH BURST CURRENT:
SELF REFRESH CURRENT: CKE
OPERATING CURRENT: Four device bank interleaving READs
(Burst = 4) with auto precharge,
t
READ, or WRITE commands
NOTE:
RC (MIN);
CK =
CK (MIN); Address and control inputs change only during Active
a: Value calculated as one module rank in this operating condition, and all other module ranks in I
b: Value calculated reflects all module ranks in this operating condition.
t
CK (MIN);
t
t
t
CK =
CK =
CK =
active; Address and control inputs changing once per
DD
t
t
t
CK (MIN); DQ, DM and DQS inputs changing once
CKE = HIGH; Address and other control inputs
CK (MIN);
CK (MIN); DQ, DM, and DQS inputs changing
;
t
RC =
Specifications and Conditions – 512MB
t
RC =
cycle. V
t
RAS (MAX);
I
t
t
OUT
RC (MIN);
CK =
0.2V
t
IN
= 0mA
RC = minimum
t
CK =
Reads; Continuous burst; One
t
= V
changing once per clock cycle
CK (MIN);
t
REF
CK =
t
t
CK (MIN);
CK =
for DQ, DQS, and DM
t
t
t
REFC =
REFC = 7.8125µs
CK (MIN); DQ, DM and
t
CK (MIN); I
t
RC allowed;
CKE = (LOW)
t
RFC (MIN)
One
OUT
14
t
t
RC =
CK =
=
SYMBOL
I
I
I
I
I
I
I
I
DD5A
I
DD4W
I
DD3N
I
I
DD2P
DD3P
DD4R
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD2F
DD5
DD6
DD7
DD0
DD1
a
a
b
b
a
b
b
b
b
a
a
b
1,032
1,392
1,432
1,432
4,080
3,312
-335
800
480
960
64
96
64
200-PIN DDR SODIMM
512MB, 1GB (x64, DR)
T
A
MAX
1,032
1,312
1,232
1,232
3,760
2,832
-262
720
400
800
+70°C; V
64
96
64
DD
DD
-26A/
1,192
1,232
1,232
3,760
2,832
-265
992
720
400
800
64
96
64
, V
2p (CKE LOW) mode.
DD
©2004 Micron Technology, Inc.
Q = +2.5V ±0.2V
UNITS NOTES
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
21, 28,
21, 28,
20, 41
20, 41
20, 41
20, 43
24, 43
20, 42
43
44
43
20
9