MT18VDDT12872AG-40BF1 Micron Technology Inc, MT18VDDT12872AG-40BF1 Datasheet - Page 21

• Manufacturer Part Number: MT18VDDT12872AG-40BF1
• Description: MODULE DDR SDRAM 1GB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDT12872AG-40BF1

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
34. The voltage levels used are derived from a mini-
35. V
36. V
37.
38.
39. During initialization, V
40. The current Micron part operates below the slow-
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
pulse width
greater than 1/3 of the cycle rate. V
V
pulse width can not be greater than 1/3 of the
cycle rate.
t
(MAX) condition.
t
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(
be equal to or less than V
V
even if V
42
supply and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
LZ (MIN) will prevail over
DQSCK (MIN) +
RPST end point and
f. The full variation in the ratio of the nominal
t
IH
IL
DD
RPST), or begins driving (
TT
(MIN) = -1.5V for a pulse width
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0 Volt.
overshoot: V
and V
may be 1.35V maximum during power up,
of series resistance is used between the V
DD
DD
DD
level and the referenced test load. In
/V
Q must track each other.
DD
3ns and the pulse width can not be
Q are 0V, provided a minimum of
t
IH
RPRE (MAX) condition.
t
LZ (MIN) will prevail over
(MAX)
t
RPRE begin point are not
DD
DD
Q, V
t
t
DQSCK (MIN) +
RPRE).
+ 0.3V. Alternatively,
= V
TT
, and V
DD
IL
Q+1.5V for a
undershoot:
3ns and the
256MB, 512MB, 1GB (x72, ECC, DR), PC3200
REF
t
RPST
must
TT
21
41. Random addressing changing and 50 percent of
42. Random addressing changing and 100 percent of
43. CKE must be active (high) during the entire time a
44. I
45. Whenever the operating frequency is altered, not
46. Leakage number reflects the worst case leakage
47. This is the DC voltage supplied at the DRAM and
48. When an input signal is HIGH or LOW, it is
data changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
driven to a valid high or low logic level. I
similar to I
address and control inputs to remain stable.
Although I
I
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
possible through the module pin, not what each
memory device contributes.
is inclusive of all noise up to 20 MHz. Any noise
above 20MHz at the DRAM generated from any
source other than the DRAM istelf may not exceed
the DC voltage range of +2.6V ±0.1V.
defined as a steady state logic HIGH or LOW.
REF later.
DD
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM UDIMM
2N specifies the DQ, DQS, and DM to be
2F is “worst case.”
DD
DD
2F, I
2F except I
DD
2N, and I
DD
DD
2Q specifies the
©2004 Micron Technology, Inc.
2Q are similar,
DD
2Q is