MT18VDDT12872AG-40BF1 Micron Technology Inc, MT18VDDT12872AG-40BF1 Datasheet - Page 9

• Manufacturer Part Number: MT18VDDT12872AG-40BF1
• Description: MODULE DDR SDRAM 1GB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDT12872AG-40BF1

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 6:
NOTE:
Table 7:
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
1. For a burst length of two, A1-Ai select the two-data-ele-
2. For a burst length of four, A2-Ai select the four-data-
3. For a burst length of eight, A3-Ai select the eight-data-
4. Whenever a boundary of the block is reached within a
5. i = 9 (256MB, 512MB);
LENGTH
BURST
ment block; A0 selects the first access within the block.
element block; A0-A1 select the first access within the
block.
element block; A0-A2 select the first access within the
block.
given sequence above, the following access wraps
within the block.
i = 9, 11 (1GB)
2
4
8
SPEED
-40B
A2
0
0
0
0
1
1
1
1
STARTING
ADDRESS
COLUMN
Burst Definition Table
CAS Latency (CL) Table
A1 A0
A1 A0
75
0
0
1
1
0
0
1
1
0
0
1
1
CL = 2
f
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ALLOWABLE OPERATING
133
ORDER OF ACCESSES WITHIN
FREQUENCY (MHZ)
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
SEQUENTIAL
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
75
0-1
1-0
CL = 2.5
f
A BURST
167 125
INTERLEAVED
256MB, 512MB, 1GB (x72, ECC, DR), PC3200
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
CL = 3
0-1
1-0
f
200
9
Operating Mode
MODE REGISTER SET command with bits A7–A11 (for
256MB), or A7–A12 (512MB, 1GB) each set to zero, and
bits A0–A6 set to the desired values. A DLL reset is ini-
tiated by issuing a MODE REGISTER SET command
with bits A7 and A9–A11 (256MB), or A7 and A9–A12
(512MB, 1GB) each set to zero, bit A8 set to one, and
bits A0–A6 set to the desired values. Although not
required by the Micron device, JEDEC specifications
recommend when a LOAD MODE REGISTER com-
mand is issued to reset the DLL, it should always be
followed by a LOAD MODE REGISTER command to
select normal operating mode.
(256MB), or A7–A12 (512MB, 1GB) are reserved for
future use and/or test modes.
COMMAND
COMMAND
COMMAND
The normal operating mode is selected by issuing a
All other combinations of values for A7–A11
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 5: CAS Latency Diagram
CK
CK
CK
184-PIN DDR SDRAM UDIMM
READ
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
T0
T0
T0
CL = 2
TRANSITIONING DATA
CL = 2.5
NOP
NOP
NOP
T1
T1
T1
CL = 3
T2
NOP
NOP
NOP
T2
T2
Test modes and
©2004 Micron Technology, Inc.
T2n
T2n
T2n
DON’T CARE
T3
NOP
NOP
NOP
T3
T3
T3n
T3n
T3n