MT18LSDT6472AG-13ED2 Micron Technology Inc, MT18LSDT6472AG-13ED2 Datasheet - Page 9
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MT18LSDT6472AG-13ED2
Manufacturer Part Number
MT18LSDT6472AG-13ED2
Description
MODULE SDRAM 512MB 168DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT18LSDT6472AG-13ED2.pdf
(26 pages)
Specifications of MT18LSDT6472AG-13ED2
Memory Type
SDRAM
Memory Size
512MB
Speed
133MHz
Package / Case
168-DIMM
Main Category
DRAM Module
Sub-category
SDRAM
Module Type
168UDIMM
Device Core Size
72b
Organization
64Mx72
Total Density
512MByte
Chip Density
256Mb
Access Time (max)
5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Operating Current
1.233A
Number Of Elements
18
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temp Range
0C to 65C
Operating Temperature Classification
Commercial
Pin Count
168
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
burst mode, and M10 and M11 are reserved for future
use. Address A12 (M12) is undefined but should be
driven LOW during loading of the mode register.
banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.
Burst Length
ented, with the burst length being programmable, as
shown in Figure 5, Mode Register Definition Diagram,
on page 9. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 1, 2,
4, or 8 locations are available for both the sequential
and the interleaved burst types, and a full-page burst is
available for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE
command to generate arbitrary burst lengths.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached, as shown in Table 7,
Burst Definition Table, on page 10. The block is
uniquely selected by A1–A9 when the burst length is
set to two; by A2–A9 when the burst length is set to
four; and by A3–A9 when the burst length is set to
eight. The remaining (least significant) address bit(s) is
(are) used to select the starting location within the
block. Full-page bursts wrap within the page if the
boundary is reached, as shown in Table 7, Burst Defini-
tion Table, on page 10.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
09005aef807b3709
SD9_18C32_64X72AG.fm - Rev. E 11/04 EN
The mode register must be loaded when all device
Read and write accesses to the SDRAM are burst ori-
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
Accesses within a given burst may be programmed
256MB (x72, ECC, SR), 512MB (x72, ECC, DR)
9
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 7, Burst
Definition Table, on page 10.
The ordering of accesses within a burst is deter-
Figure 5: Mode Register Definition
Micron Technology, Inc., reserves the right to change products or specifications without notice.
168-PIN SDRAM UDIMM
Diagram
©2004 Micron Technology, Inc.