MT36HTS51272FY-53EA2D3 Micron Technology Inc, MT36HTS51272FY-53EA2D3 Datasheet - Page 11

• Manufacturer Part Number: MT36HTS51272FY-53EA2D3
• Description: MODULE DDR2 4GB 240FBDIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36HTS51272FY-53EA2D3

• Memory Type: DDR2 SDRAM
• Memory Size: 4GB
• Speed: 533MT/s
• Package / Case: 240-FBDIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR2 Channel
SMBus Slave Interface
Channel Latency
Peak Theoretical Throughput
PDF: 09005aef822148b0/source: 09005aef82214898
HTS36C512x72F_2.fm - Rev. A 4/06 EN
The AMB DDR2 channel supports direct connection to DDR2 SDRAM devices. The
DDR2 channel supports two ranks of eight banks with 16 row/column-request, 64 data,
and eight check-bit signals. There are two copies of address and command signals to
support FBDIMM routing and electrical requirements. Four transfer bursts are driven on
the data and check-bit lines at 800 MHz.
Propagation delays can differ between read data/check-bit strobe lanes on a given
channel. Each strobe can be calibrated by hardware-state machines using WRITE/READ
trial and error. Hardware aligns the read data and check-bits to a single core clock. The
AMB provides four copies of the command clock phase references (CK[3:0]) and write
data/check-bit strobes (DQS) for each DDR2 SDRAM device nibble.
AMB support for an SMBus interface allows system access to configuration registers
independent of the FBDIMM link. The AMB will never be a master on the SMBus, only a
slave. Serial SMBus data transfer is supported at 100 KHz. SMBus access to the AMB may
be a requirement to boot and to set link strength, frequency, and other parameters
needed to ensure robust configurations. It is also required for diagnostic support when
the high-speed link is down. The SMBus address straps located on the FBDIMM
connector are used to set the unique ID.
FBDIMM channel latency is measured from the time a read request is driven on the
FBDIMM channel pins to the time when the first 16 bytes (second chunk) of read
completion data is sampled by the memory controller.
When not using variable READ latency, the latency for a specific FBDIMM on a channel
is always equal to the latency for any other FBDIMM on that channel. However, the
latency for each FBDIMM in a specific configuration with some number of FBDIMMs
installed may not be equal to the latency for each FBDIMM in a configuration with some
different number of FBDIMMs installed. As more FBDIMMs are added to the channel,
additional latency is required to read from each FBDIMM on the channel.
Because the channel is based on point-to-point interconnection of buffer components
between FBDIMMs, memory requests are required to travel through N - 1 buffers before
reaching the Nth buffer. The result is that a four-FBDIMM channel configuration will
have greater idle READ latency than a one-FBDIMM channel configuration.
The variable READ latency capability can be used to reduce latency for FBDIMMs closer
to the host. The idle latencies listed in this section are representative of what might be
achieved in typical AMB designs. Actual implementations with latencies less than the
values listed will have higher application performance and vice versa.
An FBDIMM channel transfers read completion data on the northbound data connec-
tion; 144 bits of data are transferred for every northbound data frame. This matches the
18-byte data transfer of an ECC DDR2 SDRAM device in a single DDR2 SDRAM
command clock. A DDR2 SDRAM device burst of eight from a single channel, or burst of
four from two lock-step channels, provides a total of 72 bytes of data (64 bytes plus 8
bytes ECC). The AMB frame rate matches the DDR2 SDRAM command clock because of
the fixed 6:1 ratio of the FBDIMM channel clock to the DDR2 SDRAM command clock.
240-Pin 4GB DDR2 SDRAM FBDIMM (DR, FB, x72)
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Functional Description
©2006 Micron Technology, Inc. All rights reserved.
Preliminary