MT36HTS51272FY-53EA2D3 Micron Technology Inc, MT36HTS51272FY-53EA2D3 Datasheet - Page 7

• Manufacturer Part Number: MT36HTS51272FY-53EA2D3
• Description: MODULE DDR2 4GB 240FBDIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36HTS51272FY-53EA2D3

• Memory Type: DDR2 SDRAM
• Memory Size: 4GB
• Speed: 533MT/s
• Package / Case: 240-FBDIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Description
PDF: 09005aef822148b0/source: 09005aef82214898
HTS36C512x72F_2.fm - Rev. A 4/06 EN
6. FBDIMM SPD Specification
The Micron FBDIMM adheres to the currently proposed industry specifications for
FBDIMMs. This data sheet represents a minimal subset of the FBDIMM and AMB speci-
fication details and will be revised further as the specification matures and is approved
and released. This document is to be used only as an introduction to the industry speci-
fication, which will serve as the final reference for any an all design parameters and
criteria.
Micron’s FBDIMM is a high-bandwidth, large-capacity-channel solution that has a
narrow host interface. FBDIMMs use DDR2 SDRAM devices isolated from the channel
behind a buffer on the FBDIMM. Memory-device capacity remains high and total
memory capacity scales with DDR2 SDRAM bit density.
As shown in Figure 2 on page 8, the FBDIMM channel provides a communication path
from a host controller to an array of DDR2 SDRAM devices, with the DDR2 SDRAM
devices buffered behind an AMB device. The physical isolation of the DDR2 SDRAM
devices from the channel enables the flexibility to enhance the communication path to
significantly increase reliability and availability of the memory subsystem.
Micron’s FBDIMM features a novel architecture, including the AMB that isolates the
DDR2 SDRAM devices from the channel. This single-chip AMB component, located in
the center of each FBDIMM, acts as a repeater and buffer for all signals and commands
exchanged between the host controller and DDR2 SDRAM devices, including data input
and output. The AMB communicates with the host controller and adjacent FBDIMMs
on a system board using an industry-standard, high-speed, differential, point-to-point
interface at 1.5V.
The AMB also allows buffering of memory traffic to support large memory capacities. All
memory control for the DDR2 SDRAM devices resides in the host, including memory
request initiation, timing, refresh, scrubbing, sparing, configuration access, and power
management. The AMB interface is responsible for handling channel and memory
requests to and from the local FBDIMM and for forwarding requests to other FBDIMMs
on the memory channel.
This section describes the serial presence-detect (SPD) values for FBDIMMs, refer-
enced in the SPD “Specific Features” standard document. The SPD fields indicated in
this specification will occur in the order presented in section 1.1 of the JEDEC docu-
ment. (Note that the descriptions of bytes 0 and 1 differ from those in previous SPD
standards.) Further description of byte 2 is found in Appendix A of the JEDEC
FBDIMM SPD standard. All unused entries will be coded as 0x00. All unused bits in
defined bytes will be coded as 0, except where noted.
240-Pin 4GB DDR2 SDRAM FBDIMM (DR, FB, x72)
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2006 Micron Technology, Inc. All rights reserved.
Preliminary