MT36HTS51272FY-53EA2D3 Micron Technology Inc, MT36HTS51272FY-53EA2D3 Datasheet - Page 24

• Manufacturer Part Number: MT36HTS51272FY-53EA2D3
• Description: MODULE DDR2 4GB 240FBDIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36HTS51272FY-53EA2D3

• Memory Type: DDR2 SDRAM
• Memory Size: 4GB
• Speed: 533MT/s
• Package / Case: 240-FBDIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 12:
PDF: 09005aef822148b0/source: 09005aef82214898
HTS36C512x72F_2.fm - Rev. A 4/06 EN
Parameter
MAX TX drift (resync mode)
MAX TX drift (resample mode only)
Bit error ratio
Differential Transmitter Output Specifications (Continued)
Notes:
V
TX
-
10. Pulse width measure at 0V differential.
11. One of the components that contribute to the deterioration of the return loss is the ESD
12. The termination small signal resistance; tolerance across voltages from 100mV to 400mV
13. Lane-to-lane skew at the transmitter pins for an end component.
14. Lane-to-lane skew at the transmitter pins for an intermediate component (assuming zero
15. This is a static skew. An FBDIMM component is not allowed to change its lane-to-lane phase
16. Measured from the reference clock edge to the center of the output eye. This specification
17. BER per differential lane.
CM
1. Specified at the package pins into a timing and voltage compliance test load as shown in
2. The transmitter designer should not artificially elevate the common mode in order to meet
3. This is the ratio of the VTX-DIFFp-p of the second and following bits after a transition
4. De-emphasis shall be disabled in the calibration state.
5. Includes all sources of AC common mode noise.
6. Single-ended voltages below that value that are simultaneously detected on D+ and D- are
7. The maximum value is specified to be at least (VTX-DIFFp-pL/4) + VTX-CML + (VTX-CM-ACp-
8. This number does not include the effects of SSC or reference clock jitter.
9. Defined as the expected maximum jitter for the given probability as measured in the system
R
-
TX
AC
Figure 4-2 and in steps outlined in 4.1.2.1 of the JEDEC specification. Common-mode mea-
surements to be performed using a 101010 pattern.
this specification.
divided by the VTX-DIFFp-p of the first bit after a transition.
interpreted as the EI condition.
p/2).
(TJ), less the unbounded jitter.
structure which must be carefully designed.
shall not exceed ±5W with regard to the average of the values measured at 100mV and
400mV for that pin.
Lane-to-lane skew at the receiver pins of the incoming port).
relationship after initialization.
must be met across specified voltage and temperature ranges for a single component. Drift
rate change is significantly below the tracking capability of the receiver.
-
MATCH
= ((Max |V
V
TX
-
DC
-
CM
V
= 2 x ((|R
TX
= DC
TX
T
-
T
DIFF
T
-D+
TX
X
-
Symbol
DRIFT
-
DRIFT
p-p
(AVG)
Differential Transmitter and Receiver Specifications
BER
+ V
TX
-
RESAMPLE
= 2 x |V
-
RESYNC
TX
-D+
240-Pin 4GB DDR2 SDRAM FBDIMM (DR, FB, x72)
of (|V
-D-
- R
|)/2) - ((Min |V
24
TX
TX
TX
-D+
-D-
-D+
10
Min
|)/(R
–
–
- V
-12
+ V
TX
TX
Micron Technology, Inc., reserves the right to change products or specifications without notice.
TX
-D-
-D-
-D+
TX
|
|/2)
Max
-D+
240
120
+ R
–
+ V
TX
-D-
TX
|))
-D-
Unit
ps
ps
–
|)/2)
©2006 Micron Technology, Inc. All rights reserved.
Comments, Notes
Note 16
Note 16
Note 17
Preliminary
(EQ 1)
(EQ 2)
(EQ 3)
(EQ 4)