MA240017 Microchip Technology, MA240017 Datasheet - Page 108
MA240017
Manufacturer Part Number
MA240017
Description
MODULE PLUG-IN PIC24F16KA102 PIM
Manufacturer
Microchip Technology
Series
PIC®r
Specifications of MA240017
Accessory Type
Plug-In Module (PIM) - PIC24F16KA102
Product
Microcontroller Modules
Data Bus Width
16 bit
Core Processor
PIC24F16KA102
Operating Supply Voltage
3 V to 3.6 V
Development Tools By Supplier
Integrated Development Environment, Assembler, ANSI C Compiler
Processor Series
PIC24F
Silicon Manufacturer
Microchip
Core Architecture
PIC
Core Sub-architecture
PIC24
Silicon Core Number
PIC24F
Silicon Family Name
PIC24FxxKAxx
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
Explorer 16 (DM240001 or DM240002)
For Use With
DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MA240017
Manufacturer:
MICROCHIP
Quantity:
12 000
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PIC24F16KA102 FAMILY
REGISTER 10-2:
DS39927B-page 106
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-9
bit 8
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0, HS
DSFLT
U-0
—
2:
3:
All register bits are cleared when the DSCON<DSEN> bit is set.
All register bits are reset only in the case of a POR event outside Deep Sleep mode, except bit DSPOR,
which does not reset on a POR event that is caused due to a Deep Sleep exit.
Unlike the other bits in this register, this bit can be set outside of Deep Sleep.
Unimplemented: Read as ‘0’
DSINT0: Interrupt-on-Change bit
1 = Interrupt-on-change was asserted during Deep Sleep
0 = Interrupt-on-change was not asserted during Deep Sleep
DSFLT: Deep Sleep Fault Detected bit
1 = A Fault occurred during Deep Sleep, and some Deep Sleep configuration settings may have been
0 = No Fault was detected during Deep Sleep
Unimplemented: Read as ‘0’
DSWDT: Deep Sleep Watchdog Timer Time-out bit
1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep
0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep
DSRTCC: Real-Time Clock and Calendar Alarm bit
1 = The Real-Time Clock and Calendar triggered an alarm during Deep Sleep
0 = The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep
DSMCLR: MCLR Event bit
1 = The MCLR pin was active and was asserted during Deep Sleep
0 = The MCLR pin was not active, or was active, but not asserted during Deep Sleep
Unimplemented: Read as ‘0’
DSPOR: Power-on Reset Event bit
1 = The V
0 = The V
U-0
U-0
corrupted
—
—
DSWSRC: DEEP SLEEP WAKE-UP SOURCE REGISTER
DD
DD
supply POR circuit was active and a POR event was detected
supply POR circuit was not active, or was active but did not detect a POR event
HS = Hardware Settable bit
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
R/W-0, HS
DSWDT
U-0
(2,3)
—
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0, HS
DSRTCC
U-0
—
R/W-0, HS
DSMCLR
U-0
—
© 2009 Microchip Technology Inc.
(1)
x = Bit is unknown
U-0
U-0
—
—
DSPOR
R/W-0, HS
R/W-0, HS
DSINT0
(2,3)
bit 8
bit 0
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