Z8F64210100ZDV Zilog, Z8F64210100ZDV Datasheet - Page 151
![ADAPTER ICE Z8 ENCORE 64K 44PLCC](/photos/9/2/90270/z8f64210100zdv_sml.jpg)
Z8F64210100ZDV
Manufacturer Part Number
Z8F64210100ZDV
Description
ADAPTER ICE Z8 ENCORE 64K 44PLCC
Manufacturer
Zilog
Specifications of Z8F64210100ZDV
Module/board Type
*
For Use With/related Products
Z8 Encore!™
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3402
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Table 67. SPI Diagnostic State Register (SPIDST)
PS019921-0308
BITS
FIELD
RESET
R/W
ADDR
SPI Diagnostic State Register
SCKEN
7
SSIO—Slave Select I/O
0 = SS pin configured as an input.
1 = SS pin configured as an output (Master mode only).
SSV—Slave Select Value
If SSIO = 1 and SPI configured as a Master:
0 = SS pin driven Low (0).
1 = SS pin driven High (1).
This bit has no effect if SSIO = 0 or SPI configured as a Slave.
The SPI Diagnostic State register
is a read only register used for SPI diagnostics.
SCKEN—Shift Clock Enable
0 = The internal Shift Clock Enable signal is deasserted
1 = The internal Shift Clock Enable signal is asserted (shift register is updates on next
TCKEN—Transmit Clock Enable
0 = The internal Transmit Clock Enable signal is deasserted.
1 = The internal Transmit Clock Enable signal is asserted. When this is asserted the
SPISTATE—SPI State Machine
Defines the current state of the internal SPI State Machine.
system clock)
serial data out is updated on the next system clock (MOSI or MISO).
TCKEN
6
5
(Table
4
F64H
67) provides observability of internal state. This
R
0
3
SPISTATE
Z8 Encore! XP
2
Product Specification
Serial Peripheral Interface
1
®
F64XX Series
0
137
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