MCP2515DM-PCTL Microchip Technology, MCP2515DM-PCTL Datasheet - Page 50

• Manufacturer Part Number: MCP2515DM-PCTL
• Description: BOARD DEMO FOR MCP2515
• Manufacturer: Microchip Technology
• Series: PICtail™r
• Type: Network Controller & Processorr

Specifications of MCP2515DM-PCTL

• Main Purpose: Interface, CAN Controller
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: MCP2515, MCP25020
• Primary Attributes: Stand alone CAN Controller with CAN I/O Expander
• Interface Type: CAN
• Operating Voltage: 5 V
• Product: Modules
• For Use With/related Products: MCP2515, MCP25020
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP2515
7.6.2
The REC has reached the MCU warning limit of 96.
7.6.3
The TEC has reached the MCU warning limit of 96.
7.6.4
The REC has exceeded the error-passive limit of 127
and the device has gone to error-passive state.
7.6.5
The TEC has exceeded the error-passive limit of 127
and the device has gone to error-passive state.
REGISTER 7-1:
DS21801F-page 50
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MERRE
R/W-0
RECEIVER WARNING
TRANSMITTER WARNING
RECEIVER ERROR-PASSIVE
TRANSMITTER ERROR-PASSIVE
MERRE: Message Error Interrupt Enable bit
1 = Interrupt on error during message reception or transmission
0 = Disabled
WAKIE: Wakeup Interrupt Enable bit
1 = Interrupt on CAN bus activity
0 = Disabled
ERRIE: Error Interrupt Enable bit (multiple sources in EFLG register)
1 = Interrupt on EFLG error condition change
0 = Disabled
TX2IE: Transmit Buffer 2 Empty Interrupt Enable bit
1 = Interrupt on TXB2 becoming empty
0 = Disabled
TX1IE: Transmit Buffer 1 Empty Interrupt Enable bit
1 = Interrupt on TXB1 becoming empty
0 = Disabled
TX0IE: Transmit Buffer 0 Empty Interrupt Enable bit
1 = Interrupt on TXB0 becoming empty
0 = Disabled
RX1IE: Receive Buffer 1 Full Interrupt Enable bit
1 = Interrupt when message received in RXB1
0 = Disabled
RX0IE: Receive Buffer 0 Full Interrupt Enable bit
1 = Interrupt when message received in RXB0
0 = Disabled
WAKIE
R/W-0
CANINTE – INTERRUPT ENABLE
(ADDRESS: 2Bh)
W = Writable bit
‘1’ = Bit is set
ERRIE
R/W-0
R/W-0
TX2IE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
TX1IE
7.6.6
The TEC has exceeded 255 and the device has gone
to bus-off state.
7.7
Interrupts are directly associated with one or more
status flags in the CANINTF register. Interrupts are
pending as long as one of the flags is set. Once an
interrupt flag is set by the device, the flag can not be
reset by the MCU until the interrupt condition is
removed.
Interrupt Acknowledge
BUS-OFF
R/W-0
TX0IE
© 2010 Microchip Technology Inc.
x = Bit is unknown
RX1IE
R/W-0
R/W-0
RX0IE
bit 0