AD9958/PCBZ Analog Devices Inc, AD9958/PCBZ Datasheet - Page 11

• Manufacturer Part Number: AD9958/PCBZ
• Description: BOARD EVALUATION FOR AD9958
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9958/PCBZ

• Design Resources: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) Phase Coherent FSK Modulator (CN0186)
• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Embedded: No
• Utilized Ic / Part: AD9958
• Primary Attributes: 10-Bit DAC, 32-Bit Tuning Word Width
• Secondary Attributes: 500MHz, Graphical User Interface, 2-Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Channel Control
The Channel Control window provides control of the features
that affect the AD9958 at a channel-specific level. The following
section describes the options of the Channel Control window
as they are numerically indexed in Figure 21.
1. Channel 0 and Channel 1
Use the Channel 0 and Channel 1 tabs to select which specific
channel options to configure. The AD9958 has two independent
channels: Channel <0:1>. The default channel tab setting is
Channel 0.
2. Pwr Down
Use Pwr Down to power down the digital logic (select Digital)
or the DAC circuitry (select DAC). Upon default, both of these
boxes are not selected, indicating that the digital logic and the
DAC circuitry of that channel are enabled (powered up).
3. Modulation Output Type
The Modulation Output Type list controls what type of
modulation is performed on the channel’s output. Select Phase,
Frequency, Amplitude, or None (Single Tone) depending on
which type of modulation you want. The level of modulation
for the channel is set using the Chip Level Control window
under Modulation Configuration in the Level box.
4. Linear Sweep Options
Use the Linear Sweep Options to control the linear sweep
features. Select Enable Linear Sweep to turn on the linear
sweep function and the additional associated options (see
Figure 22).
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Figure 21. Channel Control Window
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Select Linear Sweep No Dwell to enable this feature. See the
Linear Sweep No Dwell Mode section of the AD9958 data sheet
for more information regarding the no dwell feature.
When you select Load SRR @ I/O Update,
sweep ramp rate register are loaded into the sweep ramp rate
timer every time an I/O_UPDATE is sent to the device.
The Clear Sweep Accumulator and Auto Clear Sweep
Accumulator have the same basic functionality as described in
the All Channel Accumulator Control section. The difference is
that here the function is channel-specific.
See the Linear Sweep (Shaped) Modulation Mode section of the
AD9958 data sheet for a detailed explanation of this mode.
5. Pipe-Line Latency Control
When you select the Match Pipe Delays box under Pipe-Line
Latency Control, the pipeline delay for updates to frequency,
amplitude, and phase are equal, but only for the channels
operating in single tone mode. The default setting of this box is
not selected, meaning the pipeline delay for updates to
frequency, amplitude, and phase is not equal.
Figure 22.
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the contents of the
AD9958/PCB