CDB3310 Cirrus Logic Inc, CDB3310 Datasheet - Page 7

• Manufacturer Part Number: CDB3310
• Description: BOARD EVAL FOR CS3310 COL CTRL
• Manufacturer: Cirrus Logic Inc

Specifications of CDB3310

• Main Purpose: Audio, Volume Control
• Embedded: No
• Utilized Ic / Part: CS3310
• Primary Attributes: Stereo Volume Control, 0.5 dB Step Size, Serial Control
• Secondary Attributes: -95.5 dB Attenuation, +31.5 dB Gain, 0.001% THD+N, 116 dB Dynamic Range
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1000

In single device operation, volume control data is loaded into the 16-bit shift register by holding
the CS pin low for sixteen SCLK pulses and then latched on the rising edge of CS. The previous
contents of the shift-register are shifted through the register and out SDATAO during the process.
Multi-channel operation can be implemented as shown in Figure 4 by connecting the SDATAO
of device #1 to the SDATAI pin of device #2. In this manner multiple CS3310s can be loaded from
a single serial data line without complex addressing schemes. Volume control data is loaded by
holding CS low for 16 x N SCLK pulses, where N is the number of devices in the chain. The 16
bits clocked into device #1 on SCLK pulses 1-16 are clocked into device #2 on SCLK pulses 17-
32. The CS3310s are simultaneously updated on the rising edge of CS following 16 x N SCLK
pulses Notice that a 47 kohm resistor is required to terminate SDATAI, as shown in Figure 4, due
to the high impedance state of SDATAO when CS is high..
DS82F1
SDATAO
SDATAI
SCLK
CS
L0 = Left Channel Least Significant Bit
L7 = Left Channel Most Significant Bit
SDATAI is latched internally on the rising edge of SCLK
SDATAO transitions after the falling edge of SCLK
SDATAO bits reflect the data previously loaded into the CS3310
SIGNAL
SIGNAL
AUDIO
AUDIO
R7 R6 R5 R4 R3 R2 R1 R0 L7 L6 L5 L4 L3 L2 L1 L0
R7 R6 R5 R4 R3 R2 R1 R0 L7 L6 L5 L4 L3 L2 L1 L0
Figure 4. Daisy Chaining Diagram
47 k
16
16
9
9
Figure 3. Serial Port Timing
AINR
AINR
AINL
AINL
SDATAO
SDATAO
SDATAI
SDATAI
3
7
3
7
CS3310
CS3310
#1
#2
AOUTR
AOUTR
AOUTL
AOUTL
SCLK
SCLK
CS
CS
14
11
14
11
6
2
6
2
R0 = Right Channel Least Significant Bit
R7 = Right Channel Most Significant Bit
CONTROLLER
CS3310
7