Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 193

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

PS024613-0910
1. The software configures the controller for operation as a slave in 10-bit addressing
2. The master initiates a transfer, sending the first address byte. The SLAVE mode I
3. The master sends the second address byte. The SLAVE mode I
4. The software responds to the slave address match interrupt by reading the I2CISTAT
5. The master sees the Acknowledge and sends a
6. The software responds to the interrupt by reading the I2CISTAT register, clearing the
7. The master starts the data transfer by asserting SCL Low. After the I
8. After the first bit of the first data byte has been transferred, the I
9. The software responds to the transmit data interrupt by loading the next data byte into
10. The I
mode:
(a) Initialize the
(b) Optionally set the
(c) Initialize the
(d) Set
controller recognizes the start of a 10-bit address with a match to
detects the R/W bit = 0 (a Write from the master to the slave). The I
acknowledges, indicating it is available to accept the transaction.
the second address byte with the value in
the I2CISTAT register is set = 1, causing a slave address match interrupt. The
set = 0, indicating a write to the slave. If a match occurs, the I
acknowledges on the I
register, which clears the
first address byte with the R/W set to 1. The SLAVE mode I
the
SLA[9:8]
controller sets the
match interrupt. The
on the bus.
SAM
TXI
data available to transmit, the SCL is released, and the master proceeds to shift the
first data byte.
TDRE
the I2CDATA register.
Acknowledge (or Not Acknowledge, if this byte is the final data byte).
RESTART
or MASTER/SLAVE mode with 10-bit addressing.
I2CMODE register.
bit. The software loads the initial data byte into the I2CDATA register and sets the
bit in the I2CCTL register.
2
bit which asserts the transmit data interrupt.
C master shifts in the remainder of the data byte. The master transmits the
IEN
, and detects the R/W = 1 (the master reads from the slave). The slave I
= 1,
instruction followed by the first address byte with a match to
MODE
SLA[7:0]
NAK
SAM
RD
= 0 in the I
2
GCE
bit in the I2CISTAT register, which causes the slave address
field in the I
C bus, indicating it is available to accept the data.
bit is set = 1. The SLAVE mode I
SAM
bit.
bits in the I2CSLVAD register and
bit. Because the
2
C Control register.
2
C Mode register for either SLAVE ONLY mode
SLA[7:0]
RD
RESTART
Z8FMC16100 Series Flash MCU
bit = 0, no further action is required.
. If there is a match, the
instruction, followed by the
2
C controller acknowledges
2
Product Specification
C controller recognizes
2
2
C controller
C controller compares
SLA[9:8]
2
C controller sets the
SLA[9:8]
2
2
Slave Transactions
C controller
C controller has
in the
SAM
and
RD
bit in
bit is
2
2
C
C
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