KSZ8893MQL-EVAL Micrel Inc, KSZ8893MQL-EVAL Datasheet - Page 112

EVAL KIT EXPERIMENTAL KSZ8893MQL

KSZ8893MQL-EVAL

Manufacturer Part Number
KSZ8893MQL-EVAL
Description
EVAL KIT EXPERIMENTAL KSZ8893MQL
Manufacturer
Micrel Inc
Datasheet

Specifications of KSZ8893MQL-EVAL

Main Purpose
Interface, Ethernet Controller (PHY and MAC)
Embedded
No
Utilized Ic / Part
KSZ8893MQL
Primary Attributes
3 Ports, 100BASE-TX/100BASE-FX/10BASE-T, Managed
Secondary Attributes
MII, RMII, SNI, Auto MDI, MDI-X Auto Polarity Correction, LinkMD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
576-1603
Micrel, Inc.
KSZ8893MQL/MBL
Reset Circuit
The reset circuit in Figure 32 is recommended for powering up the KSZ8893MQL/MBL if reset is triggered only by
the power supply.
VCC
D1: 1N4148
D1
R 10K
KS8893M
RST
C 10uF
Figure 32. Recommended Reset Circuit
The reset circuit in Figure 33 is recommended for applications where reset is driven by another device (e.g., CPU,
FPGA, etc),.
At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the
KSZ8893MQL/MBL device. The RST_OUT_n from CPU/FPGA provides the warm reset after power up.
VCC
R 10K
D1
KS8893M
CPU/FPGA
RST
RST_OUT_n
D2
C 10uF
D1, D2: 1N4148
Figure 33. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output
December 2007
112
M9999-121007-1.5

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