KSZ8893MQL-EVAL Micrel Inc, KSZ8893MQL-EVAL Datasheet - Page 98

• Manufacturer Part Number: KSZ8893MQL-EVAL
• Description: EVAL KIT EXPERIMENTAL KSZ8893MQL
• Manufacturer: Micrel Inc

Specifications of KSZ8893MQL-EVAL

• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: No
• Utilized Ic / Part: KSZ8893MQL
• Primary Attributes: 3 Ports, 100BASE-TX/100BASE-FX/10BASE-T, Managed
• Secondary Attributes: MII, RMII, SNI, Auto MDI, MDI-X Auto Polarity Correction, LinkMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1603

Additional MIB Counter Information
“Per Port” MIB counters are designed as “read clear.” These counters will be cleared after they are read.
“All Port Dropped Packet” MIB counters are not cleared after they are accessed and do not indicate overflow or
validity; therefore, the application must keep track of overflow and valid conditions.
To read out all the counters, the best performance over the SPI bus is (160+3)*8*200 = 260ms, where there are
160 registers, 3 overheads, 8 clocks per access, at 5MHz. In the heaviest condition, the counters will overflow in 2
minutes. It is recommended that the software read all the counters at least every 30 seconds.
A high performance SPI master is also recommended to prevent counters overflow.
December 2007
2. MIB Counter Read (Read port 2 “Rx64Octets” Counter)
3. MIB Counter Read (Read “Port1 TX Drop Packets” Counter)
Then,
Then
Read reg. 128 (0x80), overflow bit [31]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
Write to reg. 121 (0x79) with 0x1c
Write to reg. 122 (0x7A) with 0x2e
Read reg. 128 (0x80), overflow bit [31]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
Write to reg. 121 (0x79) with 0x1d
Write to reg. 122 (0x7A) with 0x00
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
valid bit [30]
counter bits [29:24]
valid bit [30]
counter bits [29:24]
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// Read MIB counter selected
// Trigger the read operation
// Read MIB counter selected
// Trigger the read operation
// If bit 31 = 1, there was a counter overflow
// If bit 30 = 0, restart (reread) from this register
// If bit 31 = 1, there was a counter overflow
// If bit 30 = 0, restart (reread) from this register
M9999-121007-1.5