NBC124XXEVB ON Semiconductor, NBC124XXEVB Datasheet - Page 13

• Manufacturer Part Number: NBC124XXEVB
• Description: EVAL BOARD FOR NBC124XX
• Manufacturer: ON Semiconductor

Specifications of NBC124XXEVB

• Design Resources: NBC124XXEVB Gerber Files
• Main Purpose: Timing, PLL
• Embedded: No
• Utilized Ic / Part: NBC12429, NBC12430, NBC12439
• Primary Attributes: DIP Switch Controlled M & N Logic
• Secondary Attributes: Push Button or Externally Controlled P_Load
• Technology Type: Evaluation Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: NBC124XX
• Other names: NBC124XXEVBOS

impedance begins to look inductive and thus increases with
increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists
for frequencies well above the bandwidth of the PLL.
the resistor with an appropriate valued inductor. Figure 9
shows a 1000 mH choke. This value choke will show a
significant impedance at 10 KHz frequencies and above.
Because of the current draw and the voltage that must be
maintained on the PLL_V
inductor is required (less than 15 W). Generally, the
resistor/capacitor filter will be cheaper, easier to implement,
and provide an adequate level of supply filtering.
sub−nanosecond output edge rates and therefore a good
power supply bypassing scheme is a must. Figure 10 shows
a representative board layout for the NBC12439. There
exists many different potential board layouts and the one
pictured is but one. The important aspect of the layout in
Figure 10 is the low impedance connections between V
and GND for the bypass capacitors. Combining good quality
general purpose chip capacitors with good PCB layout
techniques will produce effective capacitor resonances at
frequencies adequate to supply the instantaneous switching
current for the NBC12439 and NBC12439A outputs. It is
imperative that low inductance chip capacitors are used. It
is equally important that the board layout not introduce any
of the inductance saved by using the leadless capacitors.
Thin interconnect traces between the capacitor and the
power plane should be avoided and multiple large vias
should be used to tie the capacitors to the buried power
planes. Fat interconnect and large vias will help to minimize
layout induced inductance and thus maximize the series
resonant point of the bypass capacitors.
NBC12439A
A higher level of attenuation can be achieved by replacing
The
NBC12439
PLL_V
V
NBC12439
CC
CC
Figure 9. Power Supply Filter
0.01 mF
R
S
= 10−15 W
22 mF
and
CC
3.3 V or
0.01 mF
5.0 V
pin, a low DC resistance
NBC12439A
3.3 V or
5.0 V
L=1000 mH
R=15 W
provide
http://onsemi.com
CC
13
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connection to the device. The oscillator is a series resonant
circuit and the voltage amplitude across the crystal is
relatively small. It is imperative that no actively switching
signals cross under the crystal as crosstalk energy coupled
to these lines could significantly impact the jitter of the
device. Special attention should be paid to the layout of the
crystal to ensure a stable, jitter free interface between the
crystal and the on−board oscillator. Note the provisions for
placing a resistor across the crystal oscillator terminals as
discussed in the crystal oscillator section of this data sheet.
design features to minimize the susceptibility to power
supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter and bypass schemes
discussed in this section should be adequate to eliminate
power supply noise−related problems in most designs.
Jitter Performance
generation and distribution. Clock jitter can be defined as the
deviation in a clock’s output transition from its ideal
position.
variation between adjacent periods over a defined number of
observed cycles. The number of cycles observed is
Note the dotted lines circling the crystal oscillator
Although the NBC12439 and NBC12439A have several
Jitter is a common parameter associated with clock
Cycle−to−Cycle Jitter (short−term) is the period
R1
Figure 10. PCB Board Layout for (PLCC−28)
Xtal
C3
R
SHUNT
C2
C1
1
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É É É
É É É
É É É
É É É
É É É
É É É
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R1 = 10−15 W
C1 = 0.01 mF
C2 = 22 mF
C3 = 0.1 mF
É É
É É
C1
= V
= GND
= Via
CC