ATA6826-DK Atmel, ATA6826-DK Datasheet - Page 5
![BOARD EVALUATION FOR ATA6826](/photos/39/38/393885/dev-kit_ata6826_sml.jpg)
ATA6826-DK
Manufacturer Part Number
ATA6826-DK
Description
BOARD EVALUATION FOR ATA6826
Manufacturer
Atmel
Specifications of ATA6826-DK
Main Purpose
Power Management, Half H-Bridge Driver (Internal FET)
Embedded
No
Utilized Ic / Part
ATA6826
Primary Attributes
3 Half H-Bridge Drivers, 1A, 2 kV ESD Protection
Secondary Attributes
Short-Circuit, Thermal & Undervoltage Protection
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
After power-on reset, the input register has the following status:
The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during
normal operation.
4834G–BCD–01/11
Bit 15 Bit 14
Bit 15 Bit 14
H
H
H
x
H
H
H
x
Bit 13
(OCS)
Bit 13
(OCS)
H
H
H
H
Bit 12
Bit 12
H
L
L
Table 3-2.
x
Bit
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Bit 11
Bit 11
H
x
L
L
Output (Status)
Bit 10
Bit 10
Status HS1
Status HS2
Status HS3
Status LS1
Status LS2
Status LS3
Output Data Protocol
Register
H
x
L
L
SCD
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OPL
PSF
TP
Bit 9
Bit 9
H
L
L
x
Bit 8
Bit 8
Function
Temperature prewarning: high = warning
High = output is on, low = output is off; not affected by SRR
High = output is on, low = output is off; not affected by SRR
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Not used
Not used
Not used
Not used
Not used
Not used
Short circuit detected: set high when at least one high-side or low-side
switch is switched off by a short-circuit condition. Bits 1 to 6 can be used
to detect the shorted switch.
Open load detected: set high, when at least one active high-side or
low-side switch sinks/sources a current below the open load threshold
current.
Power-supply fail: undervoltage at pin VS detected
H
L
L
x
Bit 7
Bit 7
H
L
L
x
(HS3)
(HS3)
Bit 6
Bit 6
L
L
L
L
(LS3)
(LS3)
Bit 5
Bit 5
L
L
L
L
(HS2)
(HS2)
Bit 4
Bit 4
L
L
L
L
Atmel ATA6826
(LS2)
(LS2)
Bit 3
Bit 3
L
L
L
L
(HS1)
(HS1)
Bit 2
Bit 2
L
L
L
L
(LS1)
(LS1)
Bit 1
Bit 1
L
L
L
L
(SRR)
(SRR)
Bit 0
Bit 0
L
L
L
L
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