CDB42518 Cirrus Logic Inc, CDB42518 Datasheet - Page 32

• Manufacturer Part Number: CDB42518
• Description: BOARD EVAL FOR CS42518 CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42518

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42518/16
• Primary Attributes: 6 Single-Ended Analog Inputs and 8 Outputs, S/PDIF Digital Audio Transmitter and Receiver
• Secondary Attributes: GUI, I2C, SPI Interfaces
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1502

32
4.6.3
SAI_SCLK
SAI_LRCK
CX_SCLK
ADCIN1/2
CX_LRCK
ADCIN1/ADCIN2 Serial Data Format
The two serial data lines which interface to the optional external ADCs, ADCIN1 and ADCIN2, support
only left-justified, 24-bit samples at 64Fs or 128Fs. This interface is not affected by any of the serial port
configuration register bit settings. These serial data lines are used when supporting One-Line Mode of
operation with external ADCs attached. If these signals are not being used, they should be tied together
and wired to GND via a pull-down resistor.
For proper operation, the CS42518 must be configured to select which SCLK/LRCK is being used to clock
the external ADCs. The EXT ADC SCLK bit in register
set accordingly. Set this bit to ‘1’ if the external ADCs are wired using the CODEC_SP clocks. If the ADCs
are wired to use the SAI_SP clocks, set this bit to ‘0’.
Left-Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample
MSB
24
-1 -2 -3 -4 -5
Figure 15. ADCIN1/ADCIN2 Serial Audio Format
64, 128 Fs
64 Fs
not supported
+5 +4
Left Channel
SCLK Rate(s)
+3 +2 +1
LSB
Single-Speed Mode, Fs= 32, 44.1, 48 kHz
Double-Speed Mode, Fs= 64, 88.2, 96 kHz
Quad-Speed Mode, Fs= 176.4, 192 kHz
“Misc Control (address 05h)” on page 51
MSB
-1 -2 -3 -4
Notes
+5 +4
Right Channel
+3 +2 +1
LSB
CS42518
DS584F1
must be