CDB42518 Cirrus Logic Inc, CDB42518 Datasheet - Page 52

• Manufacturer Part Number: CDB42518
• Description: BOARD EVAL FOR CS42518 CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42518

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42518/16
• Primary Attributes: 6 Single-Ended Analog Inputs and 8 Outputs, S/PDIF Digital Audio Transmitter and Receiver
• Secondary Attributes: GUI, I2C, SPI Interfaces
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1502

52
6.6.3
6.6.4
6.6.5
6.6.6
6.6.7
FREEZE CONTROLS (FREEZE)
INTERPOLATION FILTER SELECT (FILT_SEL)
HIGH-PASS FILTER FREEZE (HPF_FREEZE)
CODEC SERIAL PORT MASTER/SLAVE SELECT (CODEC_SP M/S)
SERIAL AUDIO INTERFACE SERIAL PORT MASTER/SLAVE SELECT (SAI_SP M/S)
Default = 0
Function:
Default = 0
Function:
Default = 0
Function:
Default = 0
Function:
Default = 0
Function:
This function will freeze the previous output of, and allow modifications to be made to, the Volume
Control (address 0Fh-16h), Channel Invert (address 17h), and Mixing Control Pair (address 18h-1Bh)
registers without the changes taking effect until the FREEZE is disabled. To make multiple changes
in these control port registers take effect simultaneously, enable the FREEZE bit, make all register
changes, then disable the FREEZE bit.
This feature allows the user to select whether the DAC interpolation filter has a fast- or slow roll-off.
For filter characteristics, please See
0 - Fast roll-off.
1 - Slow roll-off.
When this bit is set, the internal high-pass filter for the selected channel will be disabled. The current
DC offset value will be frozen and continue to be subtracted from the conversion result. See
ital Filter Characteristics” on page
In Master Mode, CX_SCLK and CX_LRCK are outputs. Internal dividers will divide the master clock
to generate the serial clock and left/right clock. In Slave Mode, CX_SCLK and CX_LRCK become in-
puts.
If the CX_SP is in Slave Mode, CX_LRCK must be present for proper device operation.
In Master Mode, SAI_SCLK and SAI_LRCK are outputs. Internal dividers will divide the master clock
to generate the serial clock and left/right clock. In Slave Mode, SAI_SCLK and SAI_LRCK become
inputs.
If the SAI_SP is in Slave Mode, SAI_LRCK must be present for proper device operation.
9.
“D/A Digital Filter Characteristics” on page
11.
CS42518
DS584F1
“A/D Dig-