CDB4265 Cirrus Logic Inc, CDB4265 Datasheet - Page 38

• Manufacturer Part Number: CDB4265
• Description: BOARD EVAL FOR CS4265 CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4265

• Main Purpose: Audio, CODEC
• Embedded: No
• Utilized Ic / Part: CS4265
• Primary Attributes: Stereo, 24-Bit, 192 kHz Sample Rate
• Secondary Attributes: Graphic User Interface, S/PDIF/ I2S / I2C / SPI Interface
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS4265
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1001

38
6.4.3
6.4.4
6.4.5
6.5
6.5.1
Reserved
7
MCLK Frequency - Address 05h
Mute ADC (Bit 2)
Function:
When this bit is set, the serial audio output of the both ADC channels is muted.
ADC High-Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter is disabled.The current DC offset value will be frozen and
continue to be subtracted from the conversion result. See
page 25.
Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for the serial audio port. Setting this bit selects Master
Mode, while clearing this bit selects Slave Mode.
Master Clock Dividers (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK signal. See
ADC_DIF
0
1
MCLK
Freq2
6
MCLK Divider
Reserved
Reserved
Left-Justified, up to 24-bit data (default)
÷ 1.5
÷ 1
÷ 2
÷ 3
÷ 4
MCLK
Freq1
5
I²S, up to 24-bit data
Table 9. ADC Digital Interface Formats
Description
Table 10. MCLK Frequency
MCLK Freq2
MCLK
Freq0
4
0
0
0
0
1
1
1
Reserved
MCLK Freq1
3
Table 10
“High-Pass Filter and DC Offset Calibration” on
0
0
1
1
0
0
1
for the appropriate settings.
Reserved
Format
0
1
2
MCLK Freq0
0
1
0
1
0
1
x
Reserved
Figure
1
5
6
CS4265
Reserved
DS657F2
0