CDB4265 Cirrus Logic Inc, CDB4265 Datasheet - Page 39
CDB4265
Manufacturer Part Number
CDB4265
Description
BOARD EVAL FOR CS4265 CODEC
Manufacturer
Cirrus Logic Inc
Specifications of CDB4265
Main Purpose
Audio, CODEC
Embedded
No
Utilized Ic / Part
CS4265
Primary Attributes
Stereo, 24-Bit, 192 kHz Sample Rate
Secondary Attributes
Graphic User Interface, S/PDIF/ I2S / I2C / SPI Interface
Description/function
Audio CODECs
Operating Supply Voltage
5 V
Product
Audio Modules
For Use With/related Products
CS4265
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
598-1001
DS657F2
6.6
6.6.1
6.6.2
6.7
6.7.1
6.8
6.8.1
Reserved
Reserved
SDINSel
7
7
7
Signal Selection - Address 06h
Channel B PGA Control - Address 07h
Channel A PGA Control - Address 08h
DAC SDIN Source (Bit 7)
Function:
This bit is used to select the serial audio data source for the DAC as shown in
Digital Loopback (Bit 1)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer to
“Internal Digital Loopback” on page
Channel B PGA Gain (Bits 5:0)
Function:
See
Channel A PGA Gain (Bits 5:0)
Function:
Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to
+12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step.
Register settings outside of the ±12 dB range are reserved and must not be used. See
ample settings.
“Channel A PGA Gain (Bits 5:0)” on page 39.
Reserved
Reserved
Reserved
6
6
6
Reserved
Gain5
Gain5
Table 12. Example Gain and Attenuation Settings
SDINSel Setting
5
5
5
Table 11. DAC SDIN Source Selection
Gain[5:0]
101000
000000
011000
0
1
Reserved
28.
Gain4
Gain4
4
4
4
DAC Data Source
Reserved
Gain3
Gain3
3
3
3
SDIN1
SDIN2
Setting
+12 dB
-12 dB
0 dB
Reserved
Gain2
Gain2
2
2
2
Table
LOOP
Gain1
Gain1
1
1
1
11.
Table 12
CS4265
Reserved
Gain0
Gain0
0
0
0
for ex-
39