LM5067EVAL National Semiconductor, LM5067EVAL Datasheet - Page 2

• Manufacturer Part Number: LM5067EVAL
• Description: NEGATIVE HOT SWAP / INRUSH CURRE
• Manufacturer: National Semiconductor

Specifications of LM5067EVAL

• Main Purpose: Power Management, Hot Swap Controller
• Utilized Ic / Part: LM5067
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

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Theory of Operation
The LM5067 provides intelligent control of the power supply
connections of a load which is to be connected to a live power
source. The two primary functions of a hot swap circuit are in-
rush current limiting during turn-on, and monitoring of the load
current for faults during normal operation. Additional functions
include Under-Voltage Lock-Out (UVLO) and Over-Voltage
Lock-Out (OVLO) to ensure voltage is supplied to the load
only when the system input voltage is within a defined range,
power limiting in the series pass FET (Q1) during turn-on, and
a Power Good logic output (PGD) to indicate the circuit status.
Upon applying the input voltage to the LM5067 (e.g., SW1 is
switched on), Q1 is initially held off for the insertion delay
(
side. At the end of the insertion delay, if the input voltage at
VIN is between the UVLO and OVLO thresholds, Q1 is turned
on in a controlled manner to limit the in-rush current. If the in-
rush current were not limited during turn-on, the current would
be high (very high!) as the load capacitors (C3, C4) charge
up, limited only by the surge current capability of the voltage
source, C7’s characteristics, and the wiring resistance (a few
milliohms). That very high current could damage the edge
connector, PC board traces, and possibly the load capacitors
receiving the high current. Additionally, the dV/dt at the load’s
input is controlled to reduce possible EMI problems.
The LM5067 limits in-rush current to a safe level using a two
step process. In the first portion of the turn-on cycle, when the
voltage differential across Q1 is highest, Q1’s power dissipa-
tion is limited to a peak of 40W by monitoring its drain current
(the voltage across R9) and its drain-to-source voltage. Their
product is maintained constant by controlling the drain current
as the drain-to-source voltage decreases (as the output volt-
age increases). This is shown in the constant power portion
≊
1470 ms) to allow ringing and transients at the input to sub-
FIGURE 2. Evaluation Board Schematic
2
of Figure 3 where the drain current is increasing to I
the drain currrent reaches the current limit threshold (5
Amps), it is then maintained constant as the output voltage
continues to increase. When the output voltage reaches the
input voltage (V
then reduces to a value determined by the load. Q1’s gate-to-
source voltage then increases to
circuit is now in normal operation mode.
Monitoring of the load current for faults during normal opera-
tion is accomplished using the current limit circuit described
above. If the load current increases to 5 Amps (50 mV across
R9), Q1’s gate is controlled to prevent the current from in-
creasing further. When current limiting takes effect, the fault
timer limits the duration of the fault. At the end of the fault
timeout period (
the load. The LM5067-2 then initiates a restart every 21 sec-
onds. The restart consists of turning on Q1 and monitoring the
load current to determine if the fault is still present. After the
fault is removed, the circuit powers up to normal operation at
the next restart.
In a sudden overload condition (e.g., the output is shorted to
ground), it is possible the current could increase faster than
the response time of the current limit circuit. In this case, the
circuit breaker sensor shuts off Q1’s gate rapidly when the
voltage across R9 reaches
duces to the current limit threshold, the current limit circuitry
then takes over.
The PGD logic level output is low during turn-on, and switches
high when the output voltage at OUT has increased to within
1.23V of the input voltage, signifying the turn-on procedure is
essentially complete. If the OUT voltage magnitude decreas-
es more than 2.5V with respect to V
switches low. The high level voltage at PGD can be any ap-
DS
≊
104 ms) Q1 is shut off, denying current to
decreases to near zero), the drain current
≊
100 mV. When the current re-
≊
13V above VEE. The
IN
due to a fault, PGD
30038802
LIM
. When