LM5067EVAL National Semiconductor, LM5067EVAL Datasheet - Page 4

• Manufacturer Part Number: LM5067EVAL
• Description: NEGATIVE HOT SWAP / INRUSH CURRE
• Manufacturer: National Semiconductor

Specifications of LM5067EVAL

• Main Purpose: Power Management, Hot Swap Controller
• Utilized Ic / Part: LM5067
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

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Circuit Parameter Changes
Current Limit
The current limit threshold is set by R9 according to the fol-
lowing equation:
If the load current increases such that the voltage across R9
reaches 50 mV, the LM5067 then modulates Q1’s gate to limit
the current to that level. This evaluation board is supplied with
a 10 mohm resistor for R9, resulting in a current limit of 5A.
To change the current limit threshold replace R9 with a resis-
tor of the required value and power capability.
Power Limit
The maximum power dissipated in Q1 during turn-on, or due
to a fault, is limited by R9 and R6according to the following
equation:
With the components supplied on the evaluation board, P
(LIM)
high, its gate is modulated to limit its drain current so the
power dissipated in Q1 does not exceed 40W. As the drain-
to-source voltage decreases, the drain current increases,
maintaining the power dissipation constant. When the drain
current reaches the current limit threshold set by R9 (5A), the
current is then maintained constant until the output voltage
reaches its final value. The current then decreases to a value
determined by the load. See Figures 3, 8, and 9.
The fault timeout period and the restart timing are determined
by the TIMER capacitor according to the following equations:
= 40W. During turn-on, when the voltage across Q1 is
t
RESTART
t
FAULT
I
LIM
= C2 x 4.7 x 10
= 50 mV/R9
= C2 x 9.4 x 10
FIGURE 4. Fault Timeout and Restart Sequence
4
6
FET
4
Each time Q1 is subjected to the maximum power limit con-
ditions it is internally stressed for a few milliseconds. For this
reason, the power limit threshold must be set lower than the
limit indicated by the FET’s SOA chart. In this evaluation
board, the power limit threshold is set at 40W, compared to
≊
sheet. The FET manufacturer should be contacted for more
information on this subject.
Insertion Time
The insertion time starts when the voltage across the LM5067
(VCC - VEE) reaches 7.7V, and its duration is equal to
During the insertion time, Q1 is held off regardless of the volt-
age at VIN. This delay allows ringing and transients at VIN to
subside before the input voltage is applied to the load via Q1.
The insertion time on this evaluation board is
Figure 7.
Fault Detection & Restart
If the load current increases to the fault level (the current limit
threshold, 5A), an internal current source charges the timing
capacitor at the TIMER pin. When the voltage at the TIMER
pin reaches 4.0V above VEE, the fault timeout period is com-
plete, and the LM5067 shuts off Q1. The restart sequence
then begins, consisting of seven cycles at the TIMER pin be-
tween 4.0V and 1.25V, as shown in Figure 4. When the
voltage at the TIMER pin reaches 0.3V during the eighth high-
to-low ramp, Q1 is turned on. If the fault is still present, the
fault timeout period and the restart sequence repeat.
The waveform at the TIMER pin can be monitored at the test
pad located at the lower left corner of C2, above TP2. In this
evaluation board, the fault timeout period is
restart time is
150W limit indicated in the Vishay SUM40N15-38 data
≊
21 seconds. See Figures 10 and 11.
t
INSERTION
= C2 x 6.67 x 10
30038804
5
≊
104 ms, and the
≊
1470 ms. See