LVDS001EVK National Semiconductor, LVDS001EVK Datasheet - Page 6

• Manufacturer Part Number: LVDS001EVK
• Description: BOARD EVALUATION DS90LV001
• Manufacturer: National Semiconductor

Specifications of LVDS001EVK

• Main Purpose: Interface, LVDS, Repeater
• Utilized Ic / Part: DS90LV001
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

In this figure, a DS90LV047A quad LVDS driver was used to drive the DS90LV001 buffer through a 10 meter
CAT5 cable. Signal 1 is the differential signal at the output of the DS90LV047A driver. Signal 2 is the differential
signal entering the DS90LV001 buffer at the end of the 10 meter cable and signal 3 is the differential output of
the DS90LV001 buffer. Note the clean re-driven signal (signal 3), this is the role of a repeater.
Demo PCB Option
Option 1: Disabling the LVDS Buffer
The DS90LV001 buffer features an enable pin. On the evaluation PCB, the active high input (EN) is routed to a
jumper (EN). The jumper provides a connection to the V
the buffer, connect the jumper to the power plane (“H”), to disable (TRI-STATE) the buffer, connect the jumper to
ground (“L”).
Note that RT4 is saved for a future use.
Plug & Play
The following simple steps should be taken to begin testing on your completed evaluation board:
1) Connect signal common (ground) to the header marked GND
2) Connect the power supply lead to the header marked VCC (3.3V)
3) Connect +13V to the circuit bias V_BIAS (depending on the resistor tolerances, this voltage should be
adjusted to ensure that the output V
resistor on top of the board…this should be +1.25V)
4) Set EN jumper to the power plane (“H”) to enable the buffer
5) Connect a complementary signal by a signal generator to the buffer input (IN- and IN+) with:
6) Connect a differential probe to test point J2 and either a differential probe to test point J3 or RG142B cables to
an SD-22 module to OUT- and OUT+. Do not attempt to connect only one output as the +13V bias voltage
assumes that both outputs are loaded with 50 Ohms.
7) View LVDS signals using the same voltage offset and volts/div settings on the scope with the TEK P6247
differential probes and/or SD-22 module and RG142B cables
Summary
This evaluation PCB provides a simple tool to evaluate how the DS90LV001 LVDS – LVDS buffer can be used to
regenerate an LVDS signal and to determine signal quality for high speed data transmission applications.
Reference Material
Additional Information available on the Internet: http://www.national.com/appinfo/lvds
DS90LV001 datasheet
LVDS Owner’s Manual
AN-905 Transmission Line RAPIDESIGNER Operation and Application Guide
AN-1187 Leadless Leadframe Package (LLP)
a) frequency = 100 MHz (200 Mbps)
b) V
c) t
d) duty cycle = 50% (square wave)
r
IL
& t
= 1.0V & V
f
= 2ns
IH
= 1.4V
OS
is +1.25V…monitor the voltage at the voltage node before the 1620 Ohm
CC
plane (“H”) or to the Ground plane (“L”). To enable
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