ISL6142/52EVAL1 Intersil, ISL6142/52EVAL1 Datasheet - Page 6

• Manufacturer Part Number: ISL6142/52EVAL1
• Description: EVAL BOARD W/CURRENT MONITOR
• Manufacturer: Intersil

Specifications of ISL6142/52EVAL1

• Main Purpose: Power Management, Hot Swap Controller
• Utilized Ic / Part: ISL6142, 6152
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

which must be physically connected to the external +5V
supply (PS2).
Other Notes
The Over-Voltage trip point (increasing supply) is set to -54V
to protect the load resistors; the R4,R5,R6 values can be
changed for other loads. A more typical value for OV is
around -71V, the high end of the range for a -48V supply
application. See the ISL6142 data sheet for more details on
how to select the resistors.
There are many test pins that can be used for meter or
oscilloscope probes. Discrete components might even be
soldered to them if necessary (see the “Board Labels”
sections).
Additional or alternative loads can be externally connected
to both the Control board and the Load board.
Individual components can be un-soldered and replaced
with alternative values, if desired. The through-hole
components on channel B make this easier.
Be sure that any added components are properly rated for
the application voltage; this is especially true for input or
output capacitors. For example, they should be rated for
100V if the full voltage range will be used.
The power good fault LED (D5A/B) is intended for display
purposes. The implementation used is not necessarily a
satisfactory solution for a production design. Aside from
being useful only with the ISL6142, the brightness varies
greatly with the supply voltage. If the signal is to be used as
a logic output, as well as drive an LED, then the voltage level
must also be compatible with the signal it drives. The jumper
JP3 disconnects the LED from the pin to separate the
functions if desired. The present circuit also clamps the
output voltage to approximately 4.5V with a 3V zener diode
(D4) which is compatible with most logic levels. Finally, the
LED provides a current path between the PWRGD pin back
to the V
desirable in the application. Referencing the LED to the
DRAIN pin doesn’t work, since under most faults, when the
FET turns off, the DRAIN will be floating.
Since the ISL6142 PWRGD output is an open-drain, pull-down
device, an LED connected to the positive supply is another
option. Since the LED will be on during normal operation, and
off during a fault, a green “OK” LED is suggested. See
“Optional Components” section for more details.
EE
pin, when the FET is off; this may not be
6
Board Components
channels; See Fig. 4 and 7)
U1 is the ISL6142 (L) or ISL6152 (H) Intersil hot plug
controller IC; the only difference between the two part
numbers is the polarity of the PWRGD/PWRGD output (pin
1). Channel A is populated with the ISL6152; channel B is
populated with the ISL6142.
R1 is the Over-Current sense resistor. I
voltage drop across this resistor exceeds 50mV the time-out
circuit will activate and the GATE will be pulled lower (to ~4V) to
regulate the current to 50mV/Rsense. If current limiting
exceeds the programmed time-out period the fault latch will be
set and the FET will be turned off. If the voltage drop across the
R1 resistor exceeds 210mV, the hard fault comparator will trip,
the FET will be momentarily turned off (timer is reset) and then
slowly turned back on for a single retry.
Q1 is the FET that switches the voltage from the input BUS
to the LOAD (D2PAK package).
R3, C2, R2, C1 control the inrush current, prevent
momentary turn-on during power-up, and keep the gate pin
from oscillating. See ISL6142/52 data sheet for more details.
C3 is the capacitor used to program the current limit time-out
period. When the Over-Current threshold is exceeded a
20µA (nominal) current source will charge the C3 capacitor
from V
CT pin exceeds the 8.5V threshold, the GATE pin will
immediately be pulled low with a 70mA pull down device, the
Over-Current latch will be set, and the FET will be turned off.
If the Over-Current condition goes away before the time-out
period expires, the CT pin will be pulled back down to V
and normal operation will resume.
R4, R5, R6, are the resistors that divide the input power
supply voltage down to the Over-Voltage (OV) and Under-
R10
Logic
Input
(-VIN+5V)
To
ADC
R1 = 0.02Ω (1%)
R2 = 10Ω (5%)
R3 = 18KΩ (5%)
R4 = 549KΩ (1%)
R5 = 6.49KΩ (1%)
Supply
Logic
EE
-48V IN
to approximately 8.5V. When the voltage on the
R4
R5
R6
R9
FIGURE 4. TYPICAL APPLICATION
GND
UV
OV
CT
FAULT
DIS
IS
OUT
C3
V
R6 = 10KΩ (1%)
R7 = R8 = 400Ω (1%)
R9 = 4.99KΩ (1%)
R10 = 5.1KΩ (10%)
C1 = 150nF (25V)
EE
IS-
R7
R1
ISL6142/ISL6152
IS+
(Same for both A and B
V
R8
DD
SENSE GATE
C1
OC
C2 = 3.3nF (100V)
C3 = 1500pF (25V)
Q1 = IRF530
CL = 100uF (100V)
RL = Equivalent load
Q1
R2
= 50 mV / R1. If the
R3 C2
PWRGD
PWRGD
DRAIN
GND
-48V OUT
CL
RL
LOAD
EE
,