SI2457FS18-EVB Silicon Laboratories Inc, SI2457FS18-EVB Datasheet - Page 44

• Manufacturer Part Number: SI2457FS18-EVB
• Description: BOARD EVAL SI2457 + SI3018 16PIN
• Manufacturer: Silicon Laboratories Inc
• Series: ISOmodem®r

Specifications of SI2457FS18-EVB

• Main Purpose: Telecom, Data Acquisition Arrangement (DAA)
• Utilized Ic / Part: Si2457
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si2457/34/15/04-Si3008
44
Register
U6C
U4F
U6E
U6F
U7A
U50
U51
U52
U53
U62
U63
U65
U66
U67
U68
U70
U71
U76
U77
U78
U79
U83
U84
U85
U86
U87
V9AGG
DAAC1
DAAC3
DAAC4
DAAC5
MOD2
PTMR
GENA
NOLN
Name
LCDN
XMTL
GEN1
GEN2
GEN3
GEN4
LCDF
NLIU
ITC1
ITC2
LIUS
SAM
FHT
CK1
LVS
IO0
IO1
Description
Flash Hook Time. Time corresponding with “!” or “&” dial modifier that the
Si2457/34/15/04 goes on-hook during a flash hook (ms units).
Loop current debounce on time (ms units).
Loop current debounce off time (ms units).
Transmit level (1 dB units)—Sets the modem data pump transmitter level.
Default level of 0 corresponds to –9.85 dBm.
Transmit level = –(9.85 + XMTL) dBm. Range = –9.85 to –48.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
No-Line threshold. If %V1 is set, NOLN sets the threshold for determination of
line present vs. line not present.
Line-in-use threshold. If %V1 is set, LIUS sets the threshold for determination
of line in use vs. line not in use.
Line-in-use/No line threshold. If %V2 is set, NLIU sets the threshold reference
for the adaptive algorithm (see %V2).
V.90 rate adjustment for Japan (1333 BPS units).
This is a bit-mapped register
Table 17. U-Register Description (Continued)
Preliminary Rev. 0.7
0xXX40
0xXX00
0x00XX
Default
0x015E
0x00C8
0x00E0
0xXF20
0x00FF
0x401E
0x01F4
0x0000
0x0000
0x0804
0x0003
0x0008
0x0000
0x2700
0x0000
0x3240
0x0000
0x0000
0x0001
0x0007
0x0000
0x0000
0x0000