LM8322EVALKIT National Semiconductor, LM8322EVALKIT Datasheet - Page 11

• Manufacturer Part Number: LM8322EVALKIT
• Description: BOARD EVALUATION LM8322
• Manufacturer: National Semiconductor

Specifications of LM8322EVALKIT

• Main Purpose: Interface, Special Purpose
• Embedded: No
• Utilized Ic / Part: LM8322
• Primary Attributes: Mobile I/O Companion with Key-Scan, I/O Expansion, PWM, Access.bus Host
• Secondary Attributes: Board has MCU for USB to PC GUI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4 DEVICE CONFIGURATION AFTER RESET
After the LM8322 has completed its reset initialization, it will
have the following internal configuration:
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•
•
•
•
•
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10.5 CONFIGURATION INPUTS
The states sampled from the CONFIG_1 and CONFIG_2 in-
puts during reset select the ACCESS.bus address used by
the LM8322, as shown in Table 4. The address occupies the
high seven bits of the first byte of a bus transaction, with the
LSB (shown as X below) indicating the direction of transfer.
When these pins are used as GPIO ports, the design must
ensure that they have the desired states during reset. For ex-
ample, a 100-kohm resistor to ground can impose a logic 0
during reset without interfering with normal operation as a
GPIO port.
10.6 INITIALIZATION
The LM8322 waits for a WRITE_CFG command from the
host. During this time, IRQ is asserted to request service from
the host. Figure 3 describes the behavior of the LM8322 fol-
lowing reset.
CONFIG_1
PWM Clock — the PWM clock source is the on-chip clock
divided by 64. This remains in effect until changed by a
host command.
Keypad Size — 3 × 3.
Digital Multiplexers — disabled.
IRQ — enabled, active low.
NOINIT Bit — set.
Debounce Time — 3 scan cycles (about 12 milliseconds).
Active Time — 500 milliseconds.
0
0
1
1
TABLE 4. Bus Address Selection
CONFIG_2
0
1
0
1
Bus Address
1000 010X
1000 011X
1000 100X
1000 101X
FIGURE 4. IRQ Reset Timing
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Figure 4 shows the timing of IRQ relative to a RESET or POR
event and the WRITE_CFG command. 100 µs after a RE-
SET or POR event, IRQ is asserted and any READ_INT
command will return an interrupt code with the NOINIT bit set.
90 µs after a WRITE_CFG command is received, IRQ is de-
asserted.
FIGURE 3. LM8322 Initialization Behavior
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