ISL12020MIRZ-EVALZ Intersil, ISL12020MIRZ-EVALZ Datasheet - Page 14

• Manufacturer Part Number: ISL12020MIRZ-EVALZ
• Description: EVAL BOARD FOR ISL12020MIRZ
• Manufacturer: Intersil

Specifications of ISL12020MIRZ-EVALZ

• Main Purpose: Timing, Real Time Clock (RTC)
• Embedded: No
• Utilized Ic / Part: ISL12020M
• Primary Attributes: 128 Bytes SRAM, Programmable Daylight Savings Time
• Secondary Attributes: I²C Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADDR. SECTION
Real Time Clock Registers
Addresses [00h to 06h]
RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW)
These registers depict BCD representations of the time.
As such, SC (Seconds) and MN (Minutes) range from 0 to
59, HR (Hour) can either be a 12-hour or 24-hour mode,
DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is
0 to 99, and DW (Day of the Week) is 0 to 6.
The DW register provides a Day of the Week status and
uses three bits DW2 to DW0 to represent the seven days
of the week. The counter advances in the cycle 0-1-2-3-
4-5-6-0-1-2-… The assignment of a numerical value to a
specific day of the week is arbitrary and may be decided
by the system software designer. The default value is
defined as “0”.
24-HOUR TIME
If the MIL bit of the HR register is “1”, the RTC uses a
24-hour format. If the MIL bit is “0”, the RTC uses a
12-hour format and HR21 bit functions as an AM/PM
indicator with a “1” representing PM. The clock defaults
to 12-hour format time with HR21 = “0”.
LEAP YEARS
Leap years add the day February 29 and are defined as
those years that are divisible by 4. Years divisible by 100
are not leap years, unless they are also divisible by 400.
This means that the year 2000 is a leap year and the
TABLE 1. REGISTER MEMORY MAP (Continued)(X INDICATES DEFAULT VARIES WITH EACH DEVICE. YELLOW
2Ch
2Dh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Eh
2Fh
ALPHAH
DSTCR
TEMP
NPPM
XT0
GPM
SHADING INDICATES THOSE BITS SHOULD NOT BE CHANGED BY THE USER) (Continued)
DstMoFd
DstDwFd
DstMoRv
DstDwRv
ALPHAH
NAME
DstDtFd
DstHrFd
DstDtRv
DstHrRv
NPPMH
NPPML
REG
GPM1
GPM2
TK0M
TK0L
XT0
14
NPPM7
GPM17
GPM27
DSTE
TK07
D
D
D
D
D
D
D
D
D
0
0
7
DstDwRvE
DstDwFdE DstWkFd12 DstWkFd11 DstWkFd10 DstDwFd12 DstDwFd11 DstDwFd10
ALP_H6
NPPM6
GPM16
GPM26
TK06
6
D
D
D
D
D
D
D
0
0
DstDtFd21
DstHrFd21
DstWkrv12 DstWkRv11 DstWkRv10 DstDwRv12 DstDwRv11 DstDwRv10
DstDtRv21
DstHrRv21
ALP_H5
NPPM5
GPM15
GPM25
TK05
5
D
D
D
0
0
ISL12020M
XDstMoRv2
DstMoFd20 DstMoFd13 DstMoFd12 DstMoFd11 DstMoFd10
DstDtFd20
DstHrFd20
DstDtRv20
DstHrRv20
ALP_H4
NPPM4
GPM14
GPM24
TK04
XT4
4
0
0
0
BIT
year 2100 is not. The ISL12020M does not correct for the
leap year in the year 2100.
Control and Status Registers
(CSR)
Addresses [07h to 0Fh]
The Control and Status Registers consist of the Status
Register, Interrupt and Alarm Register, Analog Trimming
and Digital Trimming Registers.
Status Register (SR)
The Status Register is located in the memory map at
address 07h. This is a volatile register that provides
either control or status of RTC failure (RTCF), Battery
Level Monitor (LBAT85, LBAT75), alarm trigger, Daylight
Saving Time, crystal oscillator enable and temperature
conversion in progress bit.
BUSY BIT (BUSY)
Busy Bit indicates temperature sensing is in progress. In
this mode, Alpha, Beta and ITRO registers are disabled
and cannot be accessed.
ADDR
DstMoRv13 DstMoR12v DstMoRv11 DstMoRv10
07h
DstDtFd13
DstHrFd13
DstDtRv13
DstHrRv13
ALP_H3
NPPM3
GPM13
GPM23
TK03
XT3
3
0
0
BUSY OSCF
7
TABLE 2. STATUS REGISTER (SR)
DstHrRv12
DstDtFd12
DstHrFd12
DstDtRv12
NPPM10
ALP_H2
NPPM2
GPM12
GPM22
TK02
XT2
2
0
6
DSTDJ
DstDtFd11
DstHrFd11
DstDtRv11
DstHrRv11
ALP_H1
5
NPPM1
NPPM9
GPM11
GPM21
TK01
TK09
XT1
1
ALM LVDD LBAT85 LBAT75 RTCF
4
DstDtRv10
DstHrRv10
DstDtFd10
DstHrFd10
ALP_H0
NPPM0
NPPM8
GPM10
GPM20
TK00
TK08
XT0
0
3
RANGE DEFAULT
2
00 to FF
00 to FF
00 to FF
00 to 7F
00 to FF
01 to 12
01 to 31
00 to 03
00 to 07
00 to FF
1 to 12
1 to 31
0 to 23
0 to 23
0 to 6
0 to 6
February 11, 2010
1
FN6667.4
XXh
XXh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
0