ISL12020MIRZ-EVALZ Intersil, ISL12020MIRZ-EVALZ Datasheet - Page 31

• Manufacturer Part Number: ISL12020MIRZ-EVALZ
• Description: EVAL BOARD FOR ISL12020MIRZ
• Manufacturer: Intersil

Specifications of ISL12020MIRZ-EVALZ

• Main Purpose: Timing, Real Time Clock (RTC)
• Embedded: No
• Utilized Ic / Part: ISL12020M
• Primary Attributes: 128 Bytes SRAM, Programmable Daylight Savings Time
• Secondary Attributes: I²C Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev. (Continued)
01/15/09
03/28/08
02/27/08
DATE
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REVISION
FN6667.2
FN6667.1
FN6667.0
in the quality certifications found at
31
www.intersil.com/products
For additional products, see
Added text and equations for Ibat for temp sense ON, and for relative accuracy for 1m vs 10m
interval
Added text clarifying that no compensation at Vbat<2.7V
Revised entire Daylights savings time section
Added Application Example for DST
Added requirement for Vbat>1.8V in Vbat note.
Added apps circuit to survive Vbat<1.8V
Corrected All occurrences of Alpha tables
BOLD and shade the COMPENSATION registers in the big table to
indicate they are not to be overwritten. Also Bold an advisory
in the register sections.
Fixed blank bits in register tables and in text.
Register table: Change default values for compensation to xx's,
they are different with each device.
Added Datasheet curves
Added statement to Apps section on crystal handling similar to Maxim's
tHDDAT, added 20ns min, hysteresis moved to typical, SCL/SDA rise time min
Applied Intersil standards as follows: Updated lead finish note in
ordering information, added tjc note for thermal resistance, updated
over-temp note in electrical spec table, numbered equations that were
not initially, updated POD to latest version. Cosmetic edits throughout datasheet.
1.Page 3: IDD1 - Change Max from 6.5 to 7 and 5.5 to 6.
2.Page 3: Remove &#916;ATLSB spec
3.Page 4: Hysteresis spec - Remove Min and set Typ to 0.05X VDD
4. Page 4: tHD:DAT - Change Min from 0 to 20
5. Page 12-13: For Table 1, apply the yellow shaded and bold setting to XTO and ALPHAH
registers on page 13.
6. Page 18: Eq3 - Change "BETAVALUES" to "BETA VALUES"
7. Page 26: Eq7 - Change "ppmerror" to "ppm error"
8. Page 23: Change title for Table 25 to "ALPHA HOT REGISTER"
9. Page 16: Under "Initial AT and DT setting Register (ITRO)" section, please change the value
62.6ppm to 62.5ppm.
Removed Min and Max limits for "Oscillator Initial Accuracy". Added Typ of +/-2, Replaced Note
11 with note 9.
Initial Release to web
ISL12020M
http://rel.intersil.com/reports/search.php
ISL12020M
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February 11, 2010
FN6667.4